Comparative analysis of switching losses and current ripple of continuous and discontinuous SVPWM strategies for unbalanced two‐phase four‐leg VSI Fed unsymmetrical two‐phase induction motor

Correspondence Chakrapong Charumit, Department of Electrical Engineering, Pathumwan Institute of Technology, 833 Rama 1 Rd., Wangmai, Pathumwan, Bangkok 10330, Thailand. Email: c.charumit@gmail.com Abstract This paper presents a comparative analysis of the continuous space vector pulse width modulation and the discontinuous space vector pulse width modulation in terms of the switching losses and current ripple reduction for the unbalanced two-phase four-leg voltage source inverter fed unsymmetrical two-phase induction motor. The main function of both space vector pulse width modulation strategies is to produce unbalanced two-output voltages with constant phase shift of 90 for main and auxiliary windings. The discontinuous space vector pulse width modulation principle is modified from a traditional two-phase four-leg voltage source inverter by placement of the space vectors to alternatively eliminate zero space vector in each switching sequence. As a consequence, the proposed unmodulation region or clamping zone of the discontinuous modulation strategy has 180 all the time. The experimental results illustrate the modulation waveforms of both methods, output voltage spectrum, normalized switching losses, output current ripple and inverter efficiency at high modulation index. The evaluation of the normalized average switching losses and the current ripple of the discontinuous space vector pulse width modulation method can be reduced more than that of the continuous space vector pulse width modulation method.


FIGURE 1
Proposed two-phase four-leg VSI fed U-TPIM [11][12][13][14]. For DSVPWM techniques of three-phase threeleg VSI, there are many different techniques depending on load power factor such as DPWM 0 and DPWM 2 suitable for the leading and lagging power factor load respectively [12].
There are not any publication analysing the switching loss characteristics and the current ripple for two-phase four-leg unbalanced output VSI fed U-TPIM with CSVPWM and DSVPWM techniques. The aims of this paper are to establish unbalanced two-output voltages using the four-leg VSI with CSVPWM and DSVPWM techniques to improve the performance of the U-TPIM drive. Many researches have been studied the comparative performance evaluation between twoleg, three-leg and four-leg VSIs [3][4][5]. Although, the four-leg VSI has more switching devices than two-leg and three-leg VSIs, the magnitude of two-output voltages of the four-leg VSI gives the highest DC bus utilization compared with three-leg and two-leg VSIs at the same DC bus voltage value and also FIGURE 2 Conventional location of active space vectors in d-q plane and arbitrary output voltage [15] provides the lowest two output current ripples [3,5]. These are the advantages for choosing the four-leg VSI in this research. This paper focuses on the modulating function of unbalanced space vector PWM techniques providing unbalanced output voltages for the U-TPIM. In addition, the reduction of switching losses and current ripple are investigated. For verifying the validity of the proposed method, the experimental results of modulating waveforms, switching losses, current ripple

TWO-PHASE FOUR-LEG SVPWM TOPOLOGY
The proposed main power circuit topology of a two-phase four-leg VSI fed U-TPIM consisting of eight IGBTs as switching devices is shown in Figure 1. The terminal voltages, V ao , V bo ,V co and V do , are determined as phase-leg voltages. V ab and V cd are two voltages supplied to main and auxiliary windings of the U-TPIM, respectively. Eight IGBT power switching devices have 16 possible switching states as shown in Table 1. The upper switches, S 1 , S 3 , S 5 and S 7 are assigned with either "1" or "0" to turn-on and turn-off, respectively while the lower switches S 2 , S 4 , S 6 and S 8 have the opposite status [15].
According to the corresponding output voltages in Table 1 Table 2. There are eight possible active voltage vectors (SV 1 , SV 2 , … SV 8 )and two zero voltage vectors (SV 0 , SV 9 )as illustrated in Figure 2.
In accordance with Table 2 and Figure 2, the active voltage vector is projected in a d-q plane divided into eight sectors with 45 • . The arbitrary output voltages (V o ) can be displayed in the space vector plane. Four active voltage vectors (SV 1 , SV 3 , SV 5 , SV 7 ) have a length of 2V dc whereas four active vectors (SV 2 , SV 4 , SV 6 , SV 8 ) have a length of √ 2(2V dc ). Due to the similar principle of the conventional three-phase three-leg and two-phase four-leg SVPWM [5,12,15,16] the mathematical calculation of switching times for the two-phase four-leg SVPWM method can be dealt with in the same manner as for the conventional one. The desired output space vector voltage (V o ) [6,12,15] can be expressed mathematically in terms of the average of a number of these space vectors within a switching period in each sector as, where ΔT 2 = T U 1 + T U 2 + T SV 0 + T SV 9 ; U 1 , U 2 are two basic adjacent voltage vectors; is the sampled angular position; T U 1 ,T U 2 are the active space vector times for the two basic adjacent vectors; T SV0 ,T SV9 are the zero space vector times; ΔT is the carrier period.
Generally, for a symmetrical space vector pattern, the space vector time for each zero-switching state (T SV0 , T SV9 ) is set to be equal. More detailed description for these quantities can be found in [12,15]. From Equation (1) the relationship between space vector active times and the desired output voltage for the first sector can be expressed as, It is noticed that, Using Equations (2) and (3) yields (4) According to Figure 2 and Equation (4), the condition for the maximum possible magnitude of arbitrary output voltage vector (V o ) is 2V dc , which can occur at equal to zero. Consequently, output voltage space vector (V o ) in vector form is rotated with a circular trajectory. Therefore, the maximum output voltage space vector can be expressed as, where M is the modulation index when 0 ≤ M ≤ 2, and V dc is the DC voltage of the midpoint of the DC link. Two-phase balanced output voltages of the four-leg VSI can be expressed as,

PROPOSED UNBALANCED OUTPUT SVPWM FOR TWO-PHASE FOUR-LEG INVERTERS
The purpose of this research is to develop an unbalanced output voltage two-phase four-leg VSI using continuous and discontinuous SVPWM for U-TPIM drives. For scalar and flux vector control techniques of the U-TPIM drives, these technology drives are necessary to supply the appropriate rated voltages depending on the turns ratio of the main and auxiliary windings. For increasing the starting torque and speed regulation improvement, the magnitude of the supplied voltage for  auxiliary winding is higher than main winding voltage [1,2,6,8]. The concept of the proposed unbalanced two-phase four-leg VSI is illustrated in Figure 3 the fundamental phase-leg output voltages referenced with respect to the DC bus centre tap are defined as V ao ,V bo ,V co and V do . From the relationship of the four phasor voltages in Figure 3(a), it can be written as balanced and unbalanced two output voltages in a direct and quadrature reference frame as shown in Figure 3(b,c). V ab and V cd voltages are set to be the main and auxiliary winding voltages along the d-axis and q-axis, respectively, and the phase different angle is kept at 90 • . The output space vector V o in vector form of the balanced output voltage case is shown in Figure 3(b), which is a rotating vector with a dotted line circular trajectory. According to Figure 3(c), the concept of the proposed unbalanced output voltages, the magnitude of V cd is kept constant while the magnitude of V ab is resized by multiplying the unbalanced voltage factor |A| in the range between 0-1. As a result, the arbitrary output space vector is rotated with an ellipse trajectory. Therefore, the unbalanced voltage factor |A| can be dealt within the unbalanced output voltage as follows, when 0 < |A| < 1.
The magnitude and location of the proposed SVPWM are obtained by scaling the magnitude of conventional ones by the unbalanced voltage factor |A|. As shown in Figure 4, by using a trigonometry relationship, two active vectors SV 3 and SV 7 representing the output voltage V cd are kept constant equal to 2V dc . In order to decrease the output voltage V ab , two active vectors SV 1 and SV 5 are adjusted the scaling by reducing the unbalanced output voltage factor |A|. For the sector 1, the magnitude of SV 1 has a length equal to 2V dc ∕|A|. At the same time, the magnitude and location of SV 2 is changed. It has a length equal to 2V dc ∕Bresulting from a summation of active voltage vectors, SV 1 and SV 3 . The location of the proposed active vector SV 2 is shifted from the conventional active voltage vector as shown in Figure 4, at which the active voltage vectors SV 2 and SV 4 are shifted from the conventional angle as phase angle .
When considering Figure 4, by using the trigonometry and the relationship of |A|, |B| and , the magnitude and location of active voltage vectors in sectors 1, 2, 3 and 4 can be given by, where,

FIGURE 13
Proposed two-phase four-leg VSI system

FIGURE 14
The overall system of the proposed SVPWM with two-phase induction motor drive It is noted that, the balanced output voltage occurs at |A| = 1, and the unbalanced output voltage occurs at |A| < 1. The proposed overall location of active space vector in a d-q plane and an arbitrary output voltage is shown in Figure 5.

Calculation of proposed unbalanced space vector active time
As the differences of magnitude and location of the proposed active voltage vectors were mentioned before, the unbalanced output voltages of the four-leg VSI are obtained by scaling the unbalanced voltage factor |A| and |B|.
Because of the similar principle to the conventional balanced SVPWM, the magnitude and the location of active vectors in Figure 5 are used to calculate the switching active times for unbalanced SVPWM. As illustrated in sector 1, the space vector active times (T SV 1 , T SV 2 ) in the function of |A| and |B| can be determined by the mathematical calculation as follows: The examples of calculation of the space vector active times for the sectors 1-4 are given in Table 3. The waveforms of the space vector active times over the one period of switching time at the modulation index of 2 for the balanced output voltage and unbalanced output voltages can be plotted as shown in Figure 6(a,b), respectively.

Equivalent phase-leg reference voltages of CSVPWM method
In order to implement the carrier-based space vector PWM for the two-phase four-leg VSI, the equivalent phase-leg voltage of the continuous SVPWM technique is proposed. The equivalent phase-leg voltage signals are compared with a high frequency triangular carrier to obtain PWM signals for driving upper and lower switching devices.
The pulse patterns of the phase-leg voltages with respect to the midpoint of the DC bus voltage are shown in Figure 7, that the symmetric pulse patterns of the modulation process for sector 1 in over the time interval ΔT ∕2consisting of the switching status of space vector active time T SV 1 (1000), T SV 2 (1010) and null active vectors T SV 0 (0000), T SV 9 (1111) can be arranged in Figure 7(a). Similarly, with the same process, the switching time sequence of sector 2 are T SV 0 , T SV 3 , T SV 2 and T SV 9 in a half period of switching as shown in Figure 7 As shown in Figure 7(a), phase-leg reference voltage of phase-leg-a in sector 1 can be calculated as, Substituting the space vector active times of Equations (13) and (14) in Equation (15), the equivalent reference voltage for phase-leg-a with respect to the midpoint of DC bus voltage can be written as, ] .
(16) Similarly, according to the space vector active time in Table 3, with the same process, the examples of equivalent reference voltages of four phase-leg with respect to the midpoint of DC bus voltage for sectors 1-4 can be achieved as shown in Table 4. In addition, it can be seen that the phase-leg reference voltage equations in Table 4 correspond to unbalanced voltage factors |A|and |B|, and modulation index(M ). The phase-leg reference voltage equations of the eight sectors can be plotted to be the waveforms as shown in Figure 8 when v * ao , v * bo , v * co and v * do in dashed lines are the fundamental voltage waveforms of phaseleg reference voltage in each phase-leg. Figure 8(a) shows the For the unbalanced output voltage condition, unbalanced voltage factor |A| is adjusted lower than 1. Therefore, the magnitude of V ab is lower thanV cd as shown in Figure 8(b). Moreover, both amplitude output voltages can be adjusted by scaling the modulation index in order to supply the suitable voltages for U-TPIM drives. The magnitude of the orthogonal output voltages for the proposed unbalanced two-phase voltage can be expressed as,

Equivalent phase-leg reference voltages of DSVPWM method
This section describes the proposed DSVPWM technique. The main purpose of this strategy is to reduce the switching losses and the output current ripple. Basically, the DSVPWM for twophase four-leg VSI occurs when the zero space voltage vector of either SV 0 (0000) or SV 9 (1111) is selected resulting in the removal of zero voltage vector in successive half carrier intervals [13,14]. For the proposed DSVPWM, the zero space vector time SV 0 is selected for all eight sectors as shown in the example pulse pattern of sector 1 and 2 in Figure 9. Note that the choosing of either SV 0 or SV 9 in the proposed DSVPWM gives the same results. The equation of zero space vector time SV 0 in According to Figure 9(a), the example of calculation of the phase-leg-a reference voltage for sector 1 is given by, SubstitutingT SV 1 ,T SV 2 from Equations (13) and (14) and T SV 0 from Equation (19) in Equation (20)  In the same calculation, the phase-leg average voltages normalized with the mid-point of Table 5 shows the examples of calculated phase-leg reference voltages of sectors 1-4. The waveforms of the normalized phase-leg reference voltages of eight sectors can be plotted as shown in Figure 10. The balanced output voltages at |A| = 1 and unbalanced output voltages at |A| = 0.6 are shown in Figure 10(a,b), respectively. It can be observed that the interval clamping time or unmodulated region of the proposed method is 180 • . Hence, the reduction of switching losses does not depend on the load power factor. This is a main benefit of the proposed DSVPWM technique.

Switching losses and current ripple reduction
It is known that the principle of DSVPWM technique has more advantages in terms of the switching power losses and current ripple reduction in switching devices at a high modulation index [12,14,15]. The results of switching losses reduction occur with zero space vector placement modulation strategies. As mentioned earlier, the zero space vector placement of the proposed DSVPWM is selected with T SV 0 . Consequently, the phase-leg reference voltage waveforms are clamped to −V dc during 180 • in an unmodulated region or a non-switching period as shown in Figure 10. For the switching loss reduction of the proposed DSVPWM compared with the CSVPWM method at the same carrier frequency, the DSVPWM principle provides greater the reduction in switching losses than the CSVPWM method. On the other hand, the DSVPWM principle provides an increase of output current ripple rather than CSVPWM principles. Therefore, to reduce the switching losses and output current ripple for the DSVPWM principle; it is necessary to increase the carrier frequency of DSVPWM to 1.5 times of CSVPWM [12,14,15]. However, the switching losses of the DSVPWM method must be less than the CSVPWM method. Many papers present the switching loss analysis of discontinuous modulation using normalized load current instead of the amount of real switching power loss in a power switching device [17][18][19][20][21]. As shown in Figure 1, considering the switching loss in IGBT-S 1 (upper switch: S 1 ), total average switching losses in a switching period of switching device can be evaluated from [14], P sw,loss = P on,avg + P off,avg , where, P sw,loss is the total power switching losses in a switching period; f sw is the carrier frequency of CSVPWM method and 1.5 f sw for DSVPWM method; Carrier frequency of DSVPWM is set as 1.5 times of that of CSVPWM technique. Therefore, the normalized power switching losses, including both upper and lower switching devices (S1 and S2) for phase-leg-a in overall fundamental period, of the proposed SVPWM methods depend on the current flowing switch (I sw )in which the magnitude of I sw varies with time and relates to the load current (i load ). Therefore, the normalized power switching losses of the proposed SVPWM methods depending on the absolute load current can be expressed as, Normalized switching loss:  Figure 11, the normalized absolute load current waveform of CSVPWM is the same as a full-wave rectifier waveform, while that of DSVPWM is the same as a half-wave rectifier waveform because the clamping time or clamping zone of the DSVPWM method is 180 • . As a result, the average normalized absolute load current of CSVPWM and DSVPWM are 0.64 and 0.47, respectively. The DSVPWM method provides lower calculated average normalized total power switching losses than the CSVPWM method  [22], an increase of the conduction losses under the variation of modulation index and switching frequency of both methods is insignificant whereas a change of the switching losses is significant. As a result, the conduction losses of the proposed DSVPWM are neglected [22].
In accordance with the main power circuit of the VSI fed U-TPIM as shown in Figure 1, the simulation results of the switching loss analysis for phase-leg-a in the discontinuous modulation strategy is shown in Figure 12. A control voltage or a phaseleg reference voltage of leg-a compared with a carrier waveform to be generated gate driver signals for the proposed DSVPWM method is presented in Figure 12(a). Voltage across switching device and its current flowing through switches S 1 and S 2 are shown in Figure 12(b, e). Main winding current or load current is shown in Figure 12(f). For the consideration of the switching loss analysis, the normalized average switching loss of phase lega for DSVPWM is calculated by Equation (27) and its normalized average switching loss waveform is shown in Figure 12(g). 1.5 times of the absolute load current represents the normalized average switching losses as shown in Figure 12(g). It can be seen that the interval time periods from t 0 − t 1 , t 2 − t 3 and t 4 − t 5 are modulated times and t 1 − t 2 and t 3 − t 4 are the unmodulated times or clamping zone. The normalized switching loss waveform is equal to zero at the clamping zone, and the average of its values in the overall of the fundamental period is presented as dotted line in Figure 12(g).

EXPERIMENTAL RESULTS
A diagram of the overall system for verifying the proposed CSVPWM and DSVPWM techniques is shown in Figure 13, and an experimental setup system is shown in Figure 14.
The system is composed of an unbalanced two-phase four-leg VSI using IGBTs as switching devices, and modulation signals for driving eight IGBTs are calculated and generated by the TMS320F28335 DSP experiment kit with mathematical calculation by MATLAB/Simulink. The waveforms of experimental results are displayed by a digital oscilloscope. The single-phase capacitor start and run induction motor with a rating of 370 W, 220 V, 50 Hz, 4 P and 1375 rpm modified as a U-TPIM is used for the test with the unbalanced voltage condition. Moreover, the more details of the U-TPIM parameters are presented in Appendix (Table A1).
To confirm the validity of both proposed SVPWM principles, the experiments are divided into 3 conditions as follows: (A) a test of the modulating signal generation and PWM output voltage waveform of CSVPWM and DSVPWM techniques, (B) a comparison of switching losses and output current ripple in each phase-leg of the CSVPWM and DSVPWM principles, (C) a comparison of an inverter efficiency of both techniques.

Modulating Signals and Output Voltage Waveforms
For the implementation of the unbalanced two-phase four-leg VSI fed U-TPIM, it is necessary to determine the appropriate voltage of the main winding voltage and auxiliary winding voltage so as to define the unbalanced voltage factor as mentioned in Equation (10). Using parameters of U-TPIM in Appendix (Table A1), the rated voltages of the main winding (V ab ) and auxiliary winding (V cd ) at the frequency of 50 Hz are equal to 311 V Peak and 464 V Peak , respectively. Therefore, the calculated unbalanced voltage factor according to Equation (10) is 0.67. Substituting the modulation index (M = 2) and |A| = 0.67 into Equation (17), the DC bus voltage is equal to 464 V.
The normalized phase-leg voltages of CSVPWM and DSVPWM techniques inTables 4 and 5 are calculated and generated the gate driver signals by a TMS320F28335 DSP with MATLAB/Simulink. The carrier frequency of the proposed CSVPWM and DSVPWM methods are equal to 4 and 6 kHz, respectively. Figure 15(a,b) illustrates experimental results of the normalized phase-leg reference waveforms and PWM output voltages in each phase-leg with respect to the mid-point of the DC bus voltage of the unbalanced CSVPWM case.
According to Figure 1, the experimental result waveforms of voltages across switching devices (v S1 , v S5 ), and their currents flowing through switching device (i S1 , i S5 ) waveforms at the rated load torque of the unbalanced CSVPWM method as shown in Figure 16.v S1 and i S1 are voltage across and current flowing through switching device of IGBT (S1), which is a part of the main winding branch circuit. Likewise, v S5 and i S5 are voltage across and current flowing through switching device of IGBT (S5) which is a part of the auxiliary winding branch circuit. For the experimental results of CSVPWM in Figure 16, the switching devices are switched on-off all the time.
Similarly, the experimental results of the unbalanced DSVPWM method, this proposed method can be seen that there is the unmodulated interval time corresponding with the phase-leg reference voltage waveforms as shown in Figure 17(a,b). Especially, voltage across and current flowing through switching devices of IGBT (S1 and S5) as shown in Figure 18 can confirm that the pulse patterns switch of DSVPWM have a unmodulating region or clamping time. As a result, the DSVPWM method can reduce the switching power losses lower than the CSVPWM method. Figures 19 and 20 show PWM output voltages of the fourleg VSI (Ch.-1 =V ab , Ch.-2 =V cd ; 1000 V/div) and the motor currents (Ch.-3 =i main , Ch.-4 =i aux ; 2 A/div, 5 ms/div) with a phase difference of 90 • at the rated load torque of 2.5 N m. For both motor currents, the peak currents of main and auxiliary windings are at 3 and 1.2 A, respectively. For the experimental results of the measured voltages harmonic spectrum of both the unbalanced CSVPWM and the unbalanced DSVPWM principles in terms of the mathematical analysis, the PWM output waveforms in Figures 19 and 20 are saved as CSV format by the digital oscilloscope, and analysed harmonics spectrum by MATLAB/Simulink as shown in Figure 21. A magnitude of the fundamental voltages for main and auxiliary windings for both CSVPWM and DSVPWM methods are equal to 311 and 464 V, respectively. It can be seen that the harmonic order of the first harmonic sideband of the CSVPWM method is about 80 in which the carrier and fundamental frequency are at 4 kHz and 50 Hz, respectively while the harmonic order of the first harmonic sideband of DSVPWM method is about 120 in which the carrier and fundamental frequency are 6 kHz and 50 Hz, respectively.

Normalized switching losses and current ripple comparing
The proposed normalized switching power losses in each phaseleg of CSVPWM and DSVPWM techniques can be analysed as Figures 22 and 23. The measured data of the PWM output phase-leg voltages (V ao , V bo , V co and V do ) with respect to the mid-point of the DC bus voltage, of the normalized phase-leg reference voltage, and of the current flowing through the main winding of the motor (i main ) are used for mathematically calculating by using MATLAB/Simulink. To compare the switching losses and current ripple for both techniques, the DC bus voltage and unbalanced voltage factor |A| are defined at 464 V and 0.67, respectively. Figure 22 demonstrates the results of the normalized switching losses of the CSVPWM method in each phase-leg with the carrier frequency of 4 kHz when the modulation index is set at 2; therefore, the normalized switching loss waveform is similar to the absolute load current waveform. As shown in Figure 22(a-d). the unbalanced CSVPWM for each phase-leg-a, leg-b, leg-c and leg-d gives the normalized average values of the switching losses of 1.888, 1.889, 0.778 and 0.763, respectively. Figure 23 shows the results of the normalized switching losses of the DSVPWM method in each phase-leg with the carrier frequency equal to 6 kHz, the modulation index setting at 2, and the normalized switching loss waveform, which is 1.5 times of the absolute load current waveform. As illustrated in Figure 23(a-d), the unbalanced DSVPWM for each phase-lega, leg-b, leg-c and leg-d gives the normalized average switching losses of 1.397, 1.418, 0.54 and 0.567, respectively. The average values of the normalized switching losses of each phase-leg of CSVPWM and DSVPWM can be compared in Table 6 that the proposed DSVPWM method gives lower switching losses than the CSVPWM method about 27%. Figures 24 and 25 show the output current and the comparison of the current ripple between the current flowing through the main and auxiliary windings of the CSVPWM and DSVPWM in the mean square values. The current ripples are extracted from current excluding fundamental component using MATLAB/Simulink. The DSVPWM gives current ripple lower than the CSVPWM as shown in Table 7.

Comparison of inverter efficiency for both SVPWM techniques
Inverter efficiency testing for continuous and discontinuous modulating techniques using the power meter analyser (WT1800 Precision power analyzer) as shown in Figure 13 is proposed. The U-TPIM is controlled by open loop scalar or constant voltage per Hertz control at the rated load torque. Therefore, in order to adjust the suitable voltages of both main and auxiliary windings of the U-TPIM, the voltage source inverter must be adjusted the proportion of the voltage per frequency so as to obtain constant magnetic flux of the motor. In the efficiency test condition, the fundamental frequency of the inverter is adjusted in a range between 40-50 Hz. The efficiency of the inverter for the rated voltage per Hertz adjusted in the fundamental frequency range between 40-50 Hz can be plotted as shown in Figure 26. Clearly, for a given range of the inverter frequency, the DSVPWM method gives higher efficiency than the CSVPWM about 1%.

CONCLUSION
This presented work has studied comparative analysis of switching losses and current ripple of the CSVPWM and DSVPWM techniques for the unbalanced two-phase four-leg VSI fed U-TPIM. A reduction of both normalized switching loss and current ripple parameters to improve the performance of four-leg voltage source inverter and U-TPIM drive was mainly focused. Based on the CSVPWM and DSVPWM techniques, the amplitudes of the two-phase voltage output can be controlled by the unbalanced voltage factor and the modulation index. For the unbalanced applied voltages for both windings of the U-TPIM, the main and auxiliary currents, giving the different angle at 90 • were observed. Consequently, the starting torque and the speed regulation were improved. The values of the normalized switching losses and the current ripple obtained from the CSVPWM and DSVPWM techniques were compared. The DSVPWM gave the switching loss values lower than the CSVPWM for lega, leg-b, leg-c and leg-d equal to 26.01%, 25.33%, 30.68% and 25.65%, respectively. Furthermore, the reduction of the normalized average switching losses does not depend on a change in load current power factor (pf). The current ripple of the DSVPWM was less than that of the CSVPWM for 5.73% of main current and for 7.75% of auxiliary current. The DSVPWM method gives higher inverter efficiency than the CSVPWM throughout a range of inverter frequency between 40-50 Hz. Both of the proposed SVPWMs can be applied for the variable speed drives of U-TPIM. For practical applications, the proposed unbalanced CSVPWM method is able to be employed with a range from low to middle speeds while the proposed unbalanced DSVPWM is able to be employed with the highest speed or rated speed.