A new quasi‐Z‐source switched‐boost four‐switch three‐phase inverter with independent shoot‐through and non‐shoot‐through modulation indexes

Correspondence Ahmad Salemnia, Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran Email: a_salemnia@sbu.ac.ir Abstract Four-switch three-phase inverters (FSTPI) are the cost-optimised version of two-level voltage source inverters (TL-VSI), promoted for low-power/low-voltage machine drive systems. Adding impedance-based networks to the input of conventional VSIs provides both step-up and step-down features; however, the shoot-through (ST) modulation index limits the maximum attainable modulation index. Furthermore, in FSTPI, one switching leg has two series capacitors instead of power switches. Therefore, they are exposed to the voltage imbalance problem. This paper proposes a novel step-up FSTPI with independent shoot-through and non-shoot-through (NST) modulation indexes, improved boost factor, continuous input current, and high efficiency. This topology incorporates a quasiz-source switched-boost network with independent power switches and three duty ratios that affords two active states and one shoot-through event. These features enhance the performance of this topology if compared with former FSTPI and quasi-z-source FSTPI. For evaluating the performance of this topology, simulation in MATLAB software and experiment on a prototype have been done. Simulation and experimentation results confirm the proposed topology.


INTRODUCTION
Four-switch three-phase inverters (FSTPI) is the cost-optimised form of the conventional six-switch three-phase inverters, which are widely addressed by researchers for low-power costeffective three-phase drive systems. Because of its conventional structure, most kinds of research concentrate on its control and modulation strategies [1,2]. For example, the general PWM [3], scalar PWM method [4], general space vector modulation (SVM) [5], adaptive PWM method [6], unified PWM algorithm [7], and hybrid SVM [8] have been developed for FSTPI. FSTPI is composed of four switches and two series capacitors. These two series capacitors form a separate leg, in which one phase of the load is connected to the capacitors' midpoint. Reducing two power switches, in comparison with TL-VSI, yields improving efficiency. However, when using a capacitive leg, the inverter might be exposed to the voltage imbal-This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology ance problem. Because the current of one phase comes in/out from the midpoint of this leg, the voltage of these capacitors may have different values. The voltage imbalance problem deteriorates the performance of FSTPI. Zhu, et al. [9] has introduced an adaptive method for the conventional PWM strategy in order to suppress the capacitors' voltage difference in FSTPI. A bang-bang controller was introduced by [10] selects an appropriate inverter switching state in each sampling interval according to the difference between the voltages of capacitors. Although this method is valid, the steady-state error already does not eliminate. Kazemlou and Zolghadri [11] have proposed a novel SVM. The switching times and the sectors have been obtained according to the voltage difference between the capacitors. This strategy is implemented easily by digital signal processors.
In recent years, the design of step-up inverters has received widespread attention in journals and conferences [23,24]. Amongst several presented topologies, impedance-based stepup inverters are mostly cited due to single-stage conversion, high voltage gain, lower voltage stresses on power switches, acceptable efficiency, and some intrinsic protections. In these structures, one ST event is added to the switching algorithm. The ST period limits the inverter modulation index, and this case is a constraint. Impedance-based networks have also been adapted to FSTPIs. The main challenge is to find two split series capacitors branch in the impedance network. Antal, et al. [25] have combined a z-source network with an FSTPI. This article employed the traditional z-source network. High output current THD and discontinuous input current are the main disadvantages of the proposed topology. Different z-source FSTPI based on the conventional z-source network has been presented by [26]. This article has provided a capacitor leg for FSTPI from the input source so that it divides the voltage by using two series capacitors at the input section, and consequently, one phase of the load is linked to the neutral point of these capacitors. Nevertheless, still, the modulation index is limited by the ST time. A novel quasi-z-source FSTPI topology has been presented by [27]. This circuit incorporates a traditional quasi-z-source network. The internal capacitor of the conventional quasi-z-source network has been replaced with two series capacitors, and one phase of the load has been linked to the midpoint of them. This concept has two disadvantages: the voltage difference between the output terminals and dependent modulation and ST indexes.
This paper proposed a novel step-up FSTPI with independent ST and NST modulation indexes, improved boost factor, continuous input current, and high efficiency. This topology includes a quasi-z-source switched-boost network with independent power switches and three duty ratios that provides two active states and one shoot-through event. These features improve the performance of this topology in comparison with previous z-source and quasi-z-source FSTPIs. Simulations and experiments evaluate the performance of this structure. Results confirm the proposed topology. In the following, first, the principle of the proposed inverter is investigated. Then, in Section 3, simulation and experimental results are presented and evaluated, and results are compared with other similar works. Finally, all achievements are summarised in conclusion.  THE PROPOSED TOPOLOGY Figure 1 shows three conventional step-up FSTPI, presented by [25][26][27]. In those configurations, z-source and quasi-z-source networks added to the conventional FSTPI. Each topology has some drawbacks. In Figure 1a, the converter has discontinuous input current, and the modulation and ST indexes are dependent. In Figure 1b, the modulation and ST indexes are dependent. In Figure 1c, also, the modulation and ST indexes are dependent. Figure 2 represents the proposed stepup FSTPI. Due to combining the operation of a quasi-z-source network with a switched-boost cell, the resulted configuration is called quasi-z-source switched-boost network. The overall converter is named quasi-z-source switched-boost four-switch three-phase inverter (qZSSB-FSTPI). This step-up FSTPI contains six power switches (either IGBT or MOSFET), five capacitors, three inductors, and two fast diodes. The switches Q 1 and Q 2 are complementarily turned on/off; however, they have a specific overlap time for providing ST condition. Unlike other circuits, the capacitive leg of FSTPI, the ST and NST states of the inverter are independent. In the following, the operating principle of the proposed qZSSB-FSTPI is described.

Operating principle of qZSSB-FSTPI
All components are assumed to be ideal. This converter operates in continuous current mode (CCM). Based on the switching states of Q 1 and Q 2, three equivalent circuits can be determined. Two of them relate to the NST state, and one of them corresponds to the ST state. Figure 3 depicts the equivalent circuits of these events.

Mode 1-NST state 1 (0 ≤ t < d 1 T S )
In this switching mode, the switch Q 1 turns on, diode D 2 turns off, and diode D 1 is on. According to the equivalent circuit of Figure 3a, the following expressions are obtained.

Mode 2-ST state (d 1 T S ≤ t < d 2 T S )
The next state correlates to the shoot-through state, in which the switches Q 1 and Q 2 are turned on simultaneously. Diodes D 1 and D 2 are off. Based on Figure 3b, the expressions (7)- (12) are determined. In this mode, the voltage V x is zero.

Mode 3-NST state 2 (d 2 T S ≤ t < T S )
At the beginning of this state, the Q 1 is off while Q 2 is on. As illustrated in Figure 3c, D 1 and D 2 are in forward-bias condition. Equations (7-9) is derived from the equivalent circuit of Figure 3c. In this mode, the voltage V x is equal to v C 3 . Therefore, since the NST state 1 is applied to the converter after the NST state 2, in NST state 1, the voltage of V x is also equal to v C 3 , and it is possible to replace Voltage and current waveforms of components in the above three modes have been displayed by Figure 3d for the CCM condition.
The d ST denotes the shoot-through modulation index. Also, d 1 can be written in terms of d 2 and d ST , according to Figure 3d.
From Figure 2, V pn appears across the FSTPI section, and the voltages of capacitors C 4 and C 5 are equal to the half of V pn . In Figure 4, the boost-factor function has been illustrated for different d ST and d 1 . The proposed topology has a higher voltage gain than topologies like introduced by [25][26][27], as shown in Figure 4b. If it is assumed the input power and the output power (the input of the FSTPI stage) to be identical, as expressed in (33), the relevance between the input current value and the DCbus current value is determined from (34).
The average value of the input inductor current (I L 1 ) is equal to the input current. The average value of the output inductor current (I L3 ) is equal to the output current. Moreover, the average current of L 1 and L 2 are identical. The following identities can be derived using V L = LΔI L ∕Δt .
Furthermore, by using I C = C ΔV C ∕Δt , the following results are achieved.
Equations (35-40) are used to determine appropriate values for inductors and capacitors of the proposed converter. Usually, the inductor current ripple value is chosen between 20% and 40% of the average inductor current value. Also, the capacitor voltage ripple is selected between 5% and 15% of the capacitor voltage value. Figure 4a represents the effect of d 1 and d ST on the output voltage gain of the qZSSB-FSTPI. Based on Figure 4a, the maximum achievable ST duty cycle is 0.5. In Figure 5a and Figure 5b, the sensitivity analysis of the boost-factor subject to d 1 and d 2 has been presented. For this purpose, the differential sensitivity analysis theory is applied to (30). This analysis has been executed based on (41). The derivative of the boost-factor subject to d 1 and d 2 have been calculated. Equations (42) and (43) show these derivatives. The value of d 1 specifies the amount of addi-

Sensitivity analysis
tional gain in boost-factor function, and the amount of overlap between d 1 and d 2 defines the shoot-through duty cycle. According to the boost-factor function, if d 1 =1 and d 2 = 0, then the overall gain is multiplied by 2. Consequently, the variation of d 1 has a limited impact. However, the variation of d 2 can change the amount of overlap between them, which directly affects the gain because the shoot-through event generates the main amount of gain. Table 1 lists the voltage stress value of each semiconductor based on the converter operation shown in Figure 3. Values of V C 1 , V C 2 , V C 3 , and V pn are determined from (22) and (23). The maximum current, which is passed through power

Voltage and current of power semiconductors
switches Q 1 and Q 2 , are occurred during the ST condition ((d 2d 1 )T S ). Therefore, Q 1 and Q 2 must tolerate the current value of (I L1 +I L2 ). The maximum current that is passed through D 1 is obtained from (I L1 +I L2 −I L3 ). Furthermore, diode D 2 must withstand (I L2 −I C 2 ) in its active state.

Operating principle of the FSTPI stage
FSTPI generates a switching voltage with 50 Hz frequency. The space vector modulation algorithm is applied to this stage. There are four possible switching states for the FSTPI. Capacitors' voltage imbalance problem must be considered in selecting voltage vectors. Figure 6 compares the values of switching vectors with/without voltage imbalance in DC capacitors. It should be noted that phase B is connected to the midpoint of DClink capacitors, as shown in Figure 2. Capacitors' voltage imbalance changes the magnitude and angle of V 2 (1,0) and V 4 (0,1). Also, this problem only changes the magnitude of V 1 (0,0) and sin( re f ) sin( re f ) The switching patterns in sector 1 to 4 1). This problem causes an unbalanced condition of the line-line output voltage. Table 2 organises the specifications of switching vectors, according to the voltage of capacitors C 4 and C 5 . All voltage vectors divide the -plane into four sectors. Based on the principle of the conventional SVM, each reference vector can be reproduced by using two adjacent vectors and one zero vector. However, the FSTPI does not possess any zero vector. Hence, one vector is picked as a semi-zero vector. Table 3 is used to distinguish the sector, too. Based on the voltage-second balance theory of (33), the reference vector can be rebuilt by two adjacent vectors.
In Equation (44), U 1 and U 2 are two switching vectors that are selected by considering the location of the reference vector. T 1 and T 2 define as switching times of U 1 and U 2 , respectively. Also, T 0 denotes zero switching time. Equation (44) can be solved by considering Table 2 for each sector. Results are switching times in each sector based on the voltage of capacitors C 4 and C 5 . It is assumed that (V C 4 = mV C 5 ) and (0 < m < 1). Hence, the switching times can be deduced from Equation (44), as listed in Table 3. Resulted times are applied to the FSTPI with a particular switching algorithm, as represented in Figure 7.

Efficiency analysis
The qZSSB-FSTPI incorporates six power switches and one diode. The above modeling associates with an ideal topology. In an ideal condition, the series resistance of inductors, the forward voltage of the diode, the voltage drop of the power switch, and the on-resistance of the power switch (r on ) are neglected. Generally, these parameters affect the performance of topology, especially efficiency. The overall losses of the converter equalise to the summation of switching losses, conduction losses, and deadtime losses. The switching losses, including gate-charge loss and switching on/off loss, are determined by (45).

FIGURE 9
The efficiency analysis of qZSSB circuit  Only four switches of the FSTPI stage have dead-time between their switching actions. A negligible amount of loss corresponds to dead-time loss, which is associated with dead-time in rising and falling edges (t dr , t df ). In this condition, the output current may pass through the body-diode of power switches. The following expression describes the dead-time loss. V MBD and I MBD indicate the voltage drop and the current of body-diode, respectively.
Conduction losses of the converter depend on the parasitic elements of components and power switches. The conduction loss, relevant to each switch of the FSTPI, can be obtained from (47). D denotes the duty cycle of each switch. However, the conduction loss of the components and semiconductors of the quasiz-source switched-boost stage should be determined from its loss modeling. For this purpose, Figure 8 has been taken into account. Based on Figures 8 and 3, and three switching modes of this converter, the following expressions can be established. By applying (19) and (20) to (48-54), the following results are achieved. Finally, the equation that has the loss parameters is expressed by (59). The conduction loss of the qZSSB circuit is expressed by (60). In order to bring a better analysis, a particular case is studied. It is assumed that A set of test cases have been designed to assess the effect of parasitic parameters on the efficiency and the conduction loss of the qZSSB circuit. The results of this analysis have been depicted in Figure 9. It is inferred from the results that in the design of this stage, choosing lower inductances and low loss power semiconductors are important.

Design considerations
In order to design a qZSSB-FSTPI, the following procedure is required: i. Choosing a suitable shoot-through duty-cycle by using (31). ii. Calculating the average current of each inductor by using (26)(27)(28). iii. Selecting proper values for ΔI L and ΔV C . iv. Identifying the inductances and capacitances, considering (35-40).

RESULTS AND ANALYSIS
This section presents and investigates simulation and experimental results. A low-voltage/low-power prototype has been designed in order to assess the proposed topology, its theory, and the working principle. Table 4 summarises the specifications of this prototype. In the simulation, MATLAB/Simulink software has been utilised. In this prototype, TMS320F28335PGFA digital signal processor (DSP) generates suitable PWM signals for the converter. The GW-INSTEK GDS-2074 oscilloscope has captured experimental results. Figure 10 shows the experimental setup and its components. Figure 11a illustrates the PWM signals applied to the power switches in simulation and experiments, respectively. As can be seen, the shoot-through duty cycle is equal to 0.4 and d 2 =0.8. So, based on (32), d 1 =0.4. Figure 11b presents the output voltage in simulation and experiments. The maximum value of the line voltage is about 500V, which the RMS value is 350V. It follows the reference value. Thus, the boost factor is 7. If d 1 = 0.4 and d ST = 0.4, then, according to Figure 4a, the boost factor is 7. Hence, results confirm the theory. Figure 11c displays the output line current, in which both results are identical to 0.7 Apk. Figure 11d displays the voltage stress across the power switches Q 1 and Q 2 , whenever they are off. The measured values are 352 V for both semiconductors, which are five times greater than the input voltage.
In order to compare the measured voltage stress with the theoretical values, Figure 12a and Figure 12b have been illustrated. For d 1 = 0.4 and d ST = 0.4, the voltage stress is five times further than the input voltage, as shown in Figure 12a and Figure 12b. Furthermore, other waveforms, such as the voltage of capacitors and inductors, and the voltage stresses on power diodes have been represented in Figure 13. The voltage of inductors do not lay on zero, in the whole wave; hence, their currents are changed continuously. This feature can be seen in both the laboratory results and the simulation results. Therefore, the converter operates in a CCM. Moreover, to compare the measured values for capacitors voltages with numerical values, Figure 12c has been drawn. It shows a graph, which describes how the voltage of capacitors changes with the shoot-through duty cycle. For d 1 = 0.4 and d ST = 0.4, results validate the derived values. There are some overshoots in capacitors voltage waveforms that indicate the charging events. As can be seen from Figure 13a, the voltage of L 1 is not reached to zero any time; so, the current  Figure 14. These two capacitors form one leg of the FSTPI and can be exposed to the voltage imbalance problem.
The proposed converter cannot balance the voltage of them, and as same as other references, it must be done by the employed modulation technique. As mentioned before, SVM is implemented as a modulation strategy. Sectors are determined from Table 2, and the switching times are obtained from  Table 3, which their values rely on the voltage of C 4 and C 5 . The voltage of capacitors C 4 and C 5 is equal to half of V pn that is calculated by (24). According to (24), V pn = 500. Therefore, the voltage of C 4 and C 5 are 250 V, referred by theory.
The quality of the output current and the efficiency have also been investigated. Figure 15a shows the current THD. It  is about 3.56%. Based on the harmonic analysis, carried out for the harmonic order of 200, all harmonics have been associated around the switching frequency. Thus, no filter is needed for inductive loads because THD has a standard value (<5%). Figure 15b depicts the efficiency under different output loads. This curve confirms the results of efficiency analysis in Figure 9. The losses of FSTPI section, which includes only four power switches are negligible [27]. The main contribution of four-switch three-phase inverters over the conventional sixswitch three-phase inverters is the efficiency due to reducing two power switches from the inverter leg [27]. In this case, r on = 0.0015, r L1 = r L2 = 0.01, r L3 = 0.05, V Q = 0.5, and V F = 0.4. Table 5 compares the specifications of some similar z-source FSTPI topology with the proposed quasi-z-source switched-boost FSTPI. The main advantages of the qZSSB-FSTPI in comparison with other similar converters are the continuous input current, higher boost factor with lower ST duty-ratios, semi-linear gain, independent ST and NST modulation indexes, high efficiency, and the ability to increase the number of inputs. The last feature is realised by adding another source, such as a battery, instead of capacitor C 2 [28]. Also, similar to other inverters, it is possible to implement modern control systems, such as the family of predictive controllers [29][30][31]. Table 6 compares the proposed topology with other similar topologies quantitatively. Due to the difference between the converter specifications of this paper and [25][26][27], The experimental efficiency of the proposed topology is compared with the simulated efficiency of [25][26][27]. Although the proposed  topology includes two power switches more than [25][26][27], this converter works with lower shoot-through duty cycles than [25][26][27]. Thus, it is more efficient than them. Furthermore, this converter operates with independent shoot-through and nonshoot-through modulation indexes, which this feature is not available for others. Topologies in [25,26] operate in DCM, which is not suitable for connecting to batteries, fuel cells etc.

CONCLUSION
This paper presents a quasi-z-source switched-boost fourswitch three-phase inverter. It provides continuous input current, higher boost factor with lower ST duty-ratios, semi-linear gain, independent ST and NST modulation indexes, and highefficiency compared with previous efforts. A detailed analysis has been presented and evaluated by this paper, and simula-tion and experimental results confirm that this structure operates carefully with maximum efficiency of 96%. Also, the output current THD in the proposed step-up topology is 3.56%. This converter has semi-linear gain characteristics, which yields the comfortable design of control loops.