Design, analysis, and implementation of a new high-gain P-type step-up dc/dc converter with continuous input current and common ground

Step-up converters are increasingly developed for renewable energy and storage systems in order to raise the output voltage of those resources to higher voltage levels. Conventional step-up structures, such as P-type boost converter, provide low voltage gain, and they must be cascaded with the same modules to produce higher boost factors. This conversion method reduces overall efﬁciency. Affording higher gains with lower duty cycles and single-stage conversion increase efﬁciency. This paper proposes a new step-up P-type dc/dc converter with high voltage gain even with lower duty ratios. Additionally, it has continuous input current, high efﬁciency, and common ground between the input and the output. Detailed analysis is presented, and the performance of this new topology is compared with other high-gain step-up converters. Simulations and experiments evaluate the achievements of this topology. Results prove the proposed structure.


INTRODUCTION
Step-up converters are broadly designed and developed for dc microgrid [1,2], electric vehicles [3,4], distributed generation [5], and many other applications. There are several methods to design step-up converters [6], which are grouped into six categories, as illustrated in Figure 1. Each method has its pros and cons. The switched-capacitor-based topologies like those presented in [7,8] provide high voltage gain. However, they need large number of capacitors that affect the lifetime of the converter. A similar problem also exists in switched-inductorbased topologies [9]. Transformer-based step-up converters, such as the conventional flyback, forward [10], push-pull, halfbridge, and full-bridge [11] converters, require a large turns-ratio for ultra step-up applications that increases the volume of the high-frequency transformer, and consequently it increases the cost.
Recently, a new family of boost converters has been developed, which is called impedance-based converters. These converters usually incorporate an impedance network and a switching circuit, including power switches and power diodes that provide high output voltage gain based on a specific This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2020 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology switching algorithm. Different derivatives of impedance networks, such as Z-source [12,13], quasi Z-source [8,[14][15][16][17], X-source [18], Y-source [19], Γ-source [19], and transformerbased Z-source [20], have been presented and evaluated. They are also applicable for use with all types of power electronics converters [20,21]. They provide single-stage conversion feature and high gain, but some of them may be exposed to high voltage and current stresses, low efficiency, and common-mode problem. Some articles especially concentrate on reducing the voltage and current stress of power switches in impedance-based conversion [22][23][24], fast dynamic response of impedance networks [25], decreasing the output voltage ripple of impedance-based converters [26], and the modular design of these topologies [27,28]. Recently, the active form of Z-source converters has been reviewed and cited by Nozadian et al. [29], comprising switched-boost networks (SBN) [30] and other derivations, such as embedded SBN [31] and qusi-SBN [32,33].
The topic of modular boost converters has received considerable interest. In this type, a step-up cell with a specific configuration of components is designed, and the final step-up topology is produced according to that manufactured cell, together with a    [27,28,34,35]. Those are usually extensible that yields a high gain. However, the overall efficiency is reduced if compared with the one step-up cell. As an instance, Mohammadi et al. [36] proposed an efficient P-type step-up cell that although has continuous input current, common ground, and low voltage pressure on its power switch, the resulted gain is lower than some other topologies. However, in order to reach a higher boost factor, several cells must be linked together in a cascade configuration. This method reduces the overall efficiency. If a topology provided a high boost-factor with low duty ratio and single-stage conversion, the efficiency is increased. This paper uses this rule to design a new step-up P-type dc/dc converter with high voltage gain in lower duty ratios. The continuous input current, high efficiency, and common ground between the input and the output are other features of this topology. This paper is organized as follows. Detailed analysis is described in Section 2, and the performance of this new topology is compared with other high-gain step-up converters. Simulation and experiment evaluate the performance of this topology, which will be presented in Section 3. Results prove the proposed structure. In Section 4, design considerations are presented. Finally, all achievements are summarised in Section 5.    Figure 2(a) shows a P-type-based step-up converter, which was presented by Mohammadi et al. [36]. The P-type cell has been highlighted in blue. Figure 2(b) shows another P-type cell with a coupled inductor; Figure 2(c) represents the extended ver- , where "n" and "D" denote the turns-ratio of the coupled inductor and the duty cycle of the power switch, respectively. Figure 3 represents the proposed P-type-based boost converter. A P-type cell with a coupled inductor has been used. This

PRINCIPLE OF THE IMPROVED P-TYPE STEP-UP CONVERTER
where v L1 , v L2 , v L3 , v L4 , and V LK2 indicate the instantaneous values of inductor voltage and the leakage inductance, i L1 , i L2 , i L3 , and i L4 refer to the values of inductor current, and i C 1 , i C 2 , i C 3 and i C 4 denote the instantaneous values of capacitor current. Besides, V C 1 , V C 2 , V C 3 and V C 4 show the voltages of capacitors. The i i is the input current, the "n" is the turns ratio of the coupled inductor, that is , V i is the input voltage, and I o is the load current.

Mode 2: t = [t on T s ]
In this mode, Q 1 and Q 2 are turned off. As a result, D 1 , D 2 , and D 5 conduct the current, and D 3 and D 4 are turned off, as shown in Figure 4(b). The following equations are obtained:

Calculating the ideal voltage gain function
Modes 1 and 2 are begun and finished during the intervals [0 t on ] and [t on T s ], respectively, where t on is the power switch ontime, and T s is the switching period. The effect of these events on the voltage and current of handled components is illustrated in Figure 5.
Equations (18) and (19) represent volt-second and coulombsecond identities. By applying these rules to (1)- (17) and neglecting the leakage inductance due to its small value, the average value of inductor voltage and capacitor current can be deduced. Equation (26) confirms that the input current is continuous, and as a result, this converter operates in continuous current mode (CCM): where I L1 , I L2 , I L3 , and I L4 indicate the average values of inductor current, andD and V o indicate the duty ratio and output voltage, respectively. According to the volt-second balance theory, the average value of the inductor voltage is zero in every switching interval. Therefore, the following identities are determined: Equations (27)- (29) identify the voltage of capacitors. Furthermore, capacitor C 4 is exposed to the output voltage. Therefore, V C 4 = V o . From (30), the value of output voltage gain is obtained. Accordingly, the maximum allowable duty cycle is one.
Figure 6(a) shows the voltage gain characteristics of the proposed converter. Figure 6(b) and (c) compares the gain of the proposed topology with those presented in Figure 2(a)-(c). Additionally, the discontinuous current mode (DCM) operation has been demonstrated in Figure 5(b). According to the voltage waveforms of inductors and (18), the following expressions can be obtained: Also, by calculating the average value of I D5 , the relation between D 2 and other parameters can be found as follows: where D 2 is the off-time duty ratio. This paper only focuses on the CCM operation due to the need for the continuous input current. In theory, this topology provides better voltage gain even with lower duty ratios. The extended P-type boost converter shown in Figure 2(c) requires more P-type cells to provide a higher gain that needs more components. Therefore, the implementation cost increases significantly. However, in the proposed topology, higher gains are achievable only by increasing the turns ratio of the coupled inductor.

Calculating the current and voltage of components
The coulomb-second balance theory indicates that the average value of the capacitor current is equal to zero in each switching interval. By applying this principle to (23)-(25), the average value of inductors current is calculated as follows: On the basis of the basic equations for capacitor voltage ( i C = C ΔV C Δt ), the voltage ripple values of capacitors are deduced.

Voltage stresses on semiconductors
During state 1, as displayed in Figure 4(a), diodes D 1 , D 2 , and D 5 are in reverse bias condition. D 1 is exposed to the voltage of C 1 , D 2 must tolerate V C 2 + V L3 , and D 5 is exposed to the output voltage. During state 2, as shown in Figure 4(b), diodes D 3 and D 4 and switches Q 1 and Q 2 are off. D 3 must tolerate (V C 3 − V C 1 ) during its off-state, and D 4 meets (V o − V C 1 ). The voltage stress on these components is listed in Table 1.

Converter model considering the voltage drop of diodes and power switches
In applications where the input voltage is low, neglecting the voltage drop of diodes and power switches is impossible. Consequently, the abovementioned equations are accounted for ideal conditions, and relations must be reformulated, considering the voltage drop of diodes and power switches. This section deals with this case. It is assumed that V D and V on denote the voltage drop of diodes and power switches, respectively. As a result, (1)-(4) and (10)-(12) change with the following format: By applying (18) and (19) to (48)-(51), the following relations are derived:

Small-signal model
It is possible to use (20)- (26) in order to find the small-signal model of this topology. By adding a small-signal variable to all parameters (e.g. ⟨x⟩ = X +x) and linearising the resulting equations, the following relations can be obtained: From (56)-(63), the small-signal equations can be formulated in the state-space form, as shown in (64) and (65).

Simulation results
Simulations have been done by MATLAB/Simulink software. Table 2 shows the specifications of the proposed converter. Figure 8 displays part of simulation results, including the input and output voltages, the voltage of capacitors, input current, and voltage stress on each power switch. According to Figure 8(a), the output voltage follows the desired value (60 V). As a result, the output voltage gain is 12.5. According to Figure 7(a), if the duty cycle is adjusted to 42%, then the converter reaches to gain of about 12.5. Therefore, the theoretical gain is confirmed by Figure 8(a). Figure 8(b) shows the voltage of each capacitor. This result validates Figure 7(b). Figure 8(c) represents the input current and the voltage stress on power switches.
The input current variates continuously. Therefore, the proposed converter operates in CCM. On the basis of the applied duty cycle and Table 1, the voltage stress on V Q1 and V Q2 are equalised to 14 V and 60 V, respectively; Figure 8(c) affirms these values. Figure 9 presents other relevant waveforms, which are composed of the voltage of inductors and the voltage stress on power diodes. Since the voltage of inductors has never been zero, the inductors current is continuous, as shown in Figure 9(a). The results of voltage stresses on power diodes also authenticate the summary presented in Table 1. Figure 10 shows the experimental prototype and its components. This circuit has the same elements and values as simulated topology. Generating pulse width modulated (PWM) signal is essential for driving power switches, which has been done by a simple PWM generator IC TL494. Results are captured by using a GWINSTEK GDS-2074 oscilloscope . Figure 11(a) shows the output voltage, the input voltage, and the applied PWM simultaneously. The output voltage is 60 V, when the duty cycle is adjusted to 42%. As a result, the voltage gain is 12.5, which confirms the simulation result and the graph presented in Figure 7(a). Figure 11(b) and (c) represents the amount of voltage stresses on power switches Q 1 and Q 2 , which are about 13 V and 60 V, respectively, and as can be seen, these values are identical to simulation and theoretical values. Furthermore, Figure 11(d) exhibits the voltage stresses on power diodes. Each diode has a voltage drop of 0.8 V when it is on. Figure 11(d) shows the input current waveform. It confirms that this circuit works in CCM. Figure 12 Figure 13 illustrates waveforms of inductors voltage. Since they are changing in CCM, their currents also change continuously. The voltage amplitude of inductors validates values depicted in Figure 9(a). Figure 14(a) shows the converter efficiency curve, respectively. The efficiency curve has been obtained for different output loads. The maximum achievable efficiency for this proposed topology is 94.76%. The proposed efficiency curve is obtained by experimental results. Figure 14(a) includes the overall efficiency, the converter efficiency, and the simulation results for the converter efficiency. The overall loss incorporates the efficiency of the proposed converter plus the control unit, sensors, and gate drivers. The efficiency has been calculated by using P o ∕P i ratio. According to Figure 14(a), at point (1), the converter works under no-load condition. The control loss is equal to 0.1 W, and the converter loss is about 0.159 W. Because the converter operates under no-load condition, the converter loss corresponds only to the switching losses. The converter efficiency is equal to 86.25%. However, due to above-mentioned existing losses, the total efficiency is reduced to 79.4%. This efficiency value can be compensated by choosing a lower loss control unit. It should be noted that the main scope of this article is to propose a novel topology. Therefore, the loss of the control unit has not been considered. At point (2), the output power is increased to 10 W. Therefore, the converter loss is also increased to 1.4 W due to adding conduction, core and copper losses to the proposed converter. The control loss is constant (0.15 W). At point (3), as illustrated in Figure 14, the maximum efficiency is occurred, in which the nominal output power is drawn. Figure 14(a) displays simulated efficiency. It confirms the experimental efficiency curve of the presented new topology. According to point (3), the maximum converter loss is 5% of the output power. Figure 14(b) and (c) shows the converter efficiency for different voltage and power ratings.

Comparative analysis
Many step-up topologies have been presented, providing high gain, low stresses, continuous input current, bidirectional power flow, common ground etc. Of those structures, some topologies have been compared with the proposed step-up converter. Table 3 compares them in terms of the number of power switches, the number of inductive and capacitive components, the voltage gain, and some other features. Figure 15 compares the proposed converter with other references in terms of voltage gain under the same condition. In the proposed topology, small duty ratios produce medium gains, whereas intermediate duty cycles provide high gain. The best duty cycle for this switching converter is laid between 0.25 and 0.5, which produces higher voltage gains than others. In addition, unlike some topologies, the maximum duty cycle is limited to 1, which makes this converter appropriate for a wide input voltage range.
As an instance, the converter presented in [14] has a higher gain than this converter for D > 0.42. However, its maximum duty ratio is limited to 0.5, and it does not have a common ground. The converter presented in [18] provides better gain for D < 0.25, but if "n" is set to lower values, the gain characteristics will be reduced significantly, as illustrated in Figure 15(c). Table 4 mentions the advantages and disadvantages of each structure.

DESIGN CONSIDERATIONS
In order to design the suggested structure, following stages must be considered.
1. First, a suitable duty cycle for a nominal condition of the input and output voltages must be selected. The best value is between 0.2 and 0.6 for better efficiency. In this prototype, the value of D is selected to be 0.4 for good efficiency. 2. By using (31), the proper value for "n" is determined, which in this example is identical to 1.1.
3. By using (37)-(39), the average value of inductors current is obtained. 4. By using (44)-(47) and choosing the right current ripple value for inductors, the value of inductances can be deduced. The right value for the current ripple in CCM operation is between 20% and 40% of the average inductor current. 5. Similar to stage 4, the capacitance value of capacitors can be estimated using (40)-(43). The best ripple value for capacitors is lower than 120 mVpp.

CONCLUSION
This paper proposes a new step-up dc/dc converter based on an improved P-type step-up cell. It comprises five diodes, two switches, four capacitors, two inductors, and one coupled inductor. The proposed structure reaches to high gain with this configuration. In theory, it was demonstrated that this converter performs better gain characteristics than many other boost topologies. Operating principle of the suggested topology was explained in detail. Simulation and experimental results were shown to assess the performance of this novel topology. Results and the comparative analysis validate this step-up topology. As indicated, this converter provides high voltage gain, continuous input current, high efficiency (94.76%), and common ground between the input and the output.