Research on balance control strategy of single capacitor clamped five‐level inverter clamping capacitor

Funding information National Natural Science Foundation of China, Grant/Award Number: 51767007; Key R&D projects in Jiangxi Province, Grant/Award Numbers: 20202BBEL53034, 20192BBEL50011; Jiangxi Provincial Youth Science Foundation of China, Grant/Award Number: GJJ190312 Abstract A five-level inverter composed of a single capacitor clamped three-level topology and a half-bridge is introduced, and a new SPWM control strategy for this topology is proposed. The strategy uses two modulation waves with opposite directions to modulate the positive and negative half-cycle interleaved carriers. By controlling the charging and discharging times of the clamping capacitor in each carrier cycle, the voltage balance control of the clamping capacitor is achieved. At the same time, a single-phase capacitor clamped fivelevel inverter is taken as an example to analyse the principle of the capacitor balance control strategy in detail, and to verify the correctness and feasibility of the control strategy through simulation research and experimental results.


INTRODUCTION
Multilevel inverters are widely used in medium-voltage highpower systems such as AC speed regulation and photovoltaic power generation [1][2][3]. Multilevel inverters mainly include three types of topologies: Neutral point clamp (NPC) inverter, flying capacitor (FC) inverter, and cascaded H-bridge (CHB) inverter [4][5][6]. The NPC inverter needs to control the neutral point potential, and the FC inverter needs to keep the voltage of the floating capacitor stable [7][8][9][10][11], these problems will affect the output voltage waveform quality. CHB inverter does not have the above problems, but each CHB unit needs a separate voltage source. With the increase of the number of cascaded units, CHB inverter needs a large number of power supplies and switches, which increases the cost. In order to solve the problems of NPC and FC inverters, different methods have been proposed in many papers. A carrier-based pulse width modulation scheme was proposed in [7], which can balance the neutral point voltage without introducing a zero-sequence voltage. A five-level diode-clamped H-bridge cell was introduced in [8], and a new method based on third harmonic offset injection was tested on this topology, which balances the midpoint capacitor voltage of each cell. A This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2020 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology modulation algorithm based on space vector is proposed in [9], the algorithm first selects the switching vectors according to the requirements, then selects and combines the appropriate switching vectors among them, and balances the flying capacitor voltage while synthesizing the reference voltage vector. This method can realize online calculation without looking up the table from memory or storage, which greatly reduces the amount of calculation compared with the traditional method. In literature [10], the control method is further simplified on the basis of literature [9], and a state and structure independent method is proposed to adjust the capacitor voltage. This method can be easily extended to the flying capacitor multilevel inverter with any number of cells. Literature [12,13] start with the redundant switch state of the inverter and combines the redundant switch states according to a certain rule to control the capacitor voltage. A method of time-based flying-capacitor voltage balancing control introduced in [13], the controller determines the most advantageous by judging the output of each capacitor voltage comparator, the direction of the load current and the required output voltage level switching state to achieve capacitor voltage balance. However, capacitor voltage balance cannot be achieved at a level where there is no redundant switching state. In addition, the implementation of this method requires additional sampling circuits to detect the capacitor voltage, which increases the cost. A five-level active neutral point clamp (5L-ANPC) inverter is introduced in the literature [14], in this paper, an in-depth study of the neutral point potential balance is carried out, and the relationship between the average neutral current and zero sequence voltage is obtained. Based on the carrier phase shifted pulse width modulation, the best zero sequence voltage is used to adjust the neutral point potential. However, there is still a floating capacitor in the topology, and the balance of the floating capacitor voltage is not mentioned in the paper. Literature [15] also adopts 5L-ANPC topology, and realizes the voltage self-balancing of the floating capacitor by adjusting the switching duty ratio of the two PWM signals. An open-loop NP potential balance control for 5L-NPC full-bridge grid-connected inverter (FB-GCI) proposed in [16], the balance factor k is introduced into the modulation signal and adjusted according to the calculation result of the modulation index. Therefore, although the voltage of the DC link capacitor is not sampled and controlled, the voltage of the DC link capacitor can be balanced over a wide modulation index range. Literature [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] has improved the CHB type inverter, replacing part of the DC power supply with a capacitor, and also needs to consider the problem of capacitor voltage balance. The charging bypass can keep the capacitor voltage stable, but as the cascade topology increases, the devices required for the charging bypass must also increase [17]. Controlling capacitor charge and discharge time can also achieve capacitor voltage self-balancing, but the capacitor voltage of each cascade unit in the hybrid cascade is inconsistent. In order to stabilize the capacitor voltage of each auxiliary bridge, each unit needs to have a 'current-second balance'. However, as the number of topology units increases, the control will become more complicated, which is not conducive to practical application [18]. A 7-level inverter with capacitor voltage self-balancing capability is proposed in [19], and due to the presence of switched capacitors, the topology also has boost capability. A novel clamped five-level inverter based on a bridge-type modular switched capacitor topology is proposed in [20], the composite structure in the topology can effectively reduce the use of devices, and the optimized pulse width modulation method is used to achieve voltage self-balancing of the capacitor. The topology proposed in [21,22] is based on the series connection of multiple switched capacitor units, the topology is simple and easy to expand to higher levels. In addition, the switched capacitor also has voltage self-balancing capability. A three-phase five level inverter topology with a single DC power supply was proposed in [23], the topology consists of a three-level flying capacitor inverter and a flying capacitor H-bridge. The capacitor voltage balance can be achieved by selecting the appropriate switching state. In addition, the topology also has the function of fault redundancy, if any H-bridge cell fails, it can be bypassed.
This paper introduces a single-capacitor clamped five-level Inverter, analyses its topological working principle, proposes a new SPWM control strategy, and gives the principle of clamping capacitor balance in all modulation range. A single-phase single-capacitor clamped five-level inverter is used as an example for simulation research, and the feasibility and correctness of  Figure 1 shows the topology of a single-phase capacitor clamped five-level inverter. The five-level inverter can be considered as a combination of a single-capacitor-clamped threelevel topology (red dotted line) and a two-level half-bridge, so it can be divided into two parts. First analyse the three-level topology of the red dotted line: It consists of four power switching devices and a clamping capacitor, where S 11 and S 14 pulse signals are complementary, and S 12 and S 13 pulse signals are complementary. The clamping capacitor C is a voltage clamp for the power switching device, that is, U C is equal to U dc /2, so that the voltage stresses of the four power switching devices are U dc /2, and the middle voltage level is guaranteed to be ±U dc /2. According to the characteristics of the three-level topology, these four power switching devices can choose low-voltage and high-frequency IGBTs.

TOPOLOGY OF SINGLE CAPACITOR CLAMPED FIVE-LEVEL INVERTER
Assuming that the DC-side power supply U dc is 2E, the output voltage u AN of the three-level topology (the red dotted line) can be expressed as: If the clamping capacitor voltage U C is equal to E, then Equation (1) can be simplified as: Another component of the five-level inverter in Figure 1: The two-level half bridge is composed of two complementary switching devices S 15 and S 16 . Obviously, the voltage stress it receives is the DC-side power supply voltage U dc . The function of the half bridge is to adjust the voltage polarity of the negative half-cycle output of the three-level topology, so that the entire Similarly, suppose the DC-side power supply U dc is 2E, and the half-bridge topology output voltage u ON can be expressed as: From Equations (1) and (3), the u AO expression of the output voltage of the capacitor clamped five-level inverter can be obtained: From Equations (2) and (3), we can know the expression of inverter output voltage u AO when the clamping capacitance is E From the Equations (4) and (5), the output voltage u AO of the capacitor clamped five-level inverter and the corresponding switching state can be obtained, as shown in Table 1. In addition, the state of the clamping capacitor C is also marked in Table 1, where "1" means ON, and "0" means OFF.
When the inverter output level is ±E, the redundant switching state can control the charging and discharging state of the clamping capacitor C; while outputting other levels, the clamping capacitor C is in a maintaining state.

New SPWM modulation principle
Modulation principle of SPWM dom of triangular carrier wave and sine modulation wave are improved, and a new SPWM modulation strategy is proposed, as shown in Figure 2. The advantage of this strategy is that without adding additional control circuits, only the modulation strategy itself can ensure that the charge and discharge balance of capacitor C within a triangle carrier cycle. The detailed analysis will be performed in the next section.
As can be seen from the modulation principle Figure 2, this modulation strategy uses two modulation waves: The sinusoidal modulation wave v mB , the modulation wave v mA opposite to the v mB direction, and a triangular carrier v cr , the carrier amplitude is 1. The switch S 11 pulse signal is generated by comparing the modulated wave v mA with the triangular carrier v cr , switch S 14 and S 11 pulse signals are complementary. The switch S 12 pulse signal is generated by comparing the modulated wave v mB with the triangular carrier v cr , switch S 13 and S 11 pulse signals are complementary. The pulse signal of switch S 15 is generated by the zero crossing of the modulation wave, and the pulse signals of switches S 16 and S 15 are complementary.
Modulated waves v mA , v mB can be expressed as Equations (6) and (7): In the equation, m is the amplitude modulation depth, and its range is 0 < m ≤ 1.

Analysis of clamped capacitor balance
According to the analysis in the previous section, the new SPWM modulation strategy shown in Figure 2 can make the capacitor-clamped inverter output a five-level voltage. However, it can be known from Equations (4) and (5) that the clamping capacitor voltage U C has a great influence on the inverter output voltage u AO , so it is very important to achieve the balance of the clamping capacitor. Figure 3 is the switching path of the corresponding states of the switches S 11 , S 12 , S 15 when the inverter outputs different levels. From Figure 3, it can be more clearly and intuitively found that when the switch path is switched to the inverter output E (or -E), the switch will appear redundant states. Combined with Table 1, the capacitor will only be charged and discharged when the output voltage is ±E. At other levels, the capacitor is in a maintaining state. Therefore, the use of redundant states to achieve capacitance balance is the key point of the strategy proposed in this paper. Analyse the situation when the inverter output level is E (same for output -E), there are two possible switching states of the inverter at this time: (1) S 11 S 12 S 15 = 010, (2) S 11 S 12 S 15 = 100. According to Table 1, we know that the state (1) will discharge the capacitor, and the state (2) will charge the capacitor. Assume that the total charging time of the clamping capacitor is t c and the total discharging time is t d in a triangular carrier cycle. The condition for the balance of the clamping capacitor C is t d = t c , that is, the charging and discharging times of the clamping capacitors are equal in any one carrier cycle.
Since the high-modulation depth positive half-cycle and the low-modulation depth negative half-cycle capacitor charge and discharge are the same, the high-modulation depth negative half-cycle and the low-modulation depth positive half-cycle capacitor charge and discharge are the same. Therefore, it is only necessary to provide the charge and discharge conditions of the capacitor under different modulation depths in the positive half cycle. Figure 4 shows the charging and discharging of the capacitor in the positive half cycle.
First, analyse the charge and discharge states of the capacitor in the case of Figure 4(a). It can be known from Figure 3 that the maintain charge inverter output voltage is converted between E and 2E within a triangular carrier period T c . It can be known from Figure 4(a) that when 0 < t ≤ T c /2, the carrier can be expressed by a linear function as: Substituting v mA = v cr into Equation (8), we get Similarly, substituting v mB = v cr into Equation (8), we get Combining Equations (6) and (7), it can be obtained in the positive half cycle According to Equations (9, 10, 11), According to the symmetry of the triangular carrier, it is known that the discharge time exists: t d1 = t d2 . Combining Equation (12), we can know that there is the following relationship between the charge and discharge time of the capacitor in a triangle carrier.
It can be seen from Equation (13) that under high modulation depth, the clamping capacitor C has the same charge and discharge time in one carrier cycle. Figure 4(b) shows the charging and discharging of the clamp capacitor in one carrier cycle under low modulation depth. With reference to Figure 3, at this time, the inverter output voltage is converted between 0 and E, which is in line with the phenomenon of level reduction under low modulation depth. The analysis of low modulation depth is consistent with high modulation depth, and can also obtain: t d1 + t d2 = t c . Figure 5 is a simplified clamp capacitor charging and discharging circuit, where R is the load, R ESR is the equivalent series resistance of the capacitor, and R on is the on-resistance of the switch.
According to Figure 5(a), the calculation formula of the clamp capacitor charging current i 1 is According to Figure 5(b), the calculation formula of the clamp capacitor discharging current i 2 is (15) If the carrier period is very small, then the voltage fluctuation of the capacitor is very small in a carrier period. When U c < U dc /2, combining Equations (14) and (15), it can be clearly seen that the charging current and the discharging current are not equal in this carrier cycle, and the charging current is greater than the discharging current, that is, i 1 > i 2 . For the clamp capacitor, the average current in this carrier cycle is not zero, the capacitor voltage must rise. When U c > U dc /2, the charging current is smaller than the discharging current, the capacitor voltage should drop. According to the above analysis, when the capacitor voltage is unbalanced, the charge and discharge current of clamp capacitor will be different. When the capacitor voltage is lower than U dc /2, the charging current is greater than the discharge current, and the capacitor voltage rises. When the capacitor voltage is higher than U dc /2, the charging current is less than the discharge current, and the capacitor voltage decreases. The final result is that the capacitor voltage will remain near U dc /2.
In summary, this modulation strategy can achieve selfbalancing of capacitor voltage within the all modulation range.

Clamp capacitor pre-charge
Before balancing control of the clamping capacitor, it needs to be pre-charged to 1/2 of the DC-side power supply. There are two methods: (1) Pre-charging using external circuits, but it will increase costs. (2) Use the topology itself for pre-charging. According to Table 1, the switching states S 11 S 12 S 15 = 100 and S 11 S 12 S 15 = 011 can charge the clamping capacitor as shown in Figure 6, capacitors can be pre-charged with these two switching states. In summary, choose method 2 to charge the capacitor. When the inverter starts running, the charging procedure uses two switching states S 11 S 12 S 15 = 100 and S 11 S 12 S 15 = 011 to charge the capacitor. After a delay, switch to the control program of the capacitor balance modulation strategy proposed in this paper.

SIMULATION ANALYSIS OF SPWM CONTROL STRATEGY BASED ON DUAL MODULATION WAVE
In order to verify the feasibility of the SPWM control strategy based on dual modulation wave proposed, a simulation model of single capacitor clamped five-level inverter was established in Matlab/Simulink for verification, the simulation parameters are shown in Table 2. Figure 7 shows the inverter output waveform and clamping capacitor voltage waveform under three loads when the   modulation depth is 0.9. u AO is the waveform of the inverter output phase voltage, u o is the waveform at both ends of the resistor after filtering, U C is the clamping capacitor voltage, and i o is the inverter output current. As can be seen from Figure 7, although the load characteristics are different, when the modulation depth is 0.9, U C is maintained at 12 V, which is half of the DC-side voltage source, u AO is a standard five-level voltage waveform, which shows that the modulation strategy proposed in this paper implements capacitor voltage balance. Figure 8 shows the output waveform and clamping capacitor voltage waveform of the inverter under three load conditions when the modulation depth is 0.5. It can be seen from Figure 8 that at a low modulation depth, the inverter output phase voltage u AO drops to three levels, and the clamping capacitor voltage U C remains at 12V. According to Figures 7 and 8, it can be known that the modulation strategy proposed in this paper can achieve clamping capacitor voltage balance at each modulation depth. Figure 9 is a spectrum diagram of phase voltages with modulation depths of 0.9 and 0.5, respectively. As can be seen from the figure, the phase voltage harmonics are mainly distributed Fundamental (50Hz) = 21.59 , THD= 33.32% around twice the carrier frequency. Figure 9(a) is the phase voltage spectrum analysis chart when the modulation depth is 0.9. At this time, the fundamental voltage amplitude of the phase voltage is 21.61 V and the THD is 33.27%. When the modulation depth is 0.5, the spectrum is shown in Figure 9(b), and the phase voltage fundamental wave amplitude is 12.02 V. Since the output voltage drops to three levels, the THD increases to 51.88%. According to the spectrum of the inverter output phase voltage, the equivalent switching frequency of the modulation strategy proposed in this paper is twice the carrier frequency.

EXPERIMENTAL VERIFICATION OF SPWM CONTROL STRATEGY BASED ON DUAL MODULATION WAVE
A single-capacitor clamped five-level inverter platform was established for experimental verification. This platform uses DSP (TMS320F28335) for control, as shown in Figure 10. To ensure that the experiments and simulations are consistent, the experimental parameters are the same as the simulation parameters, and will not be repeated here. Figure 11 is the process of pre-charging the clamping capacitor after the inverter starts when the modulation depth is 0.9. When the inverter outputs ±E level, the output voltage is affected by the capacitor voltage. When the capacitor voltage is not equal to U dc /2, the two switching states of output +E, one output voltage is U dc − U c and the other output voltage is U c , similar situation when outputting -E. Therefore, the level inconsistency will occur during the transient process of capacitor charging, as shown in Figure 11. It can be seen from the figure that when the clamping capacitor voltage U C increases from about 2 to 7 V, the "±E" level of the phase voltage u AO   Figure 12 shows that when the modulation depth is 0.9, the inverter enters steady state and outputs waveforms under three different loads. Among them, U C is the voltage waveform of the clamp capacitor, u AO is the phase voltage waveform, u o is the waveform at both ends of the resistor after filtering, and i o is the inverter output current waveform. It can be seen from Figure 12 that under different loads, the phase voltage waveforms output by the inverter are all five levels. At this time, the clamp capacitor voltage U C is stable at 12 V. The voltage waveform u o across the resistor and the filtered current i o waveform approach a sine wave, which is basically consistent with the simulation Figure 7. It shows that under high modulation depth, the clamping capacitor achieves voltage self-balancing. Figure 13 shows the phase voltage spectrum when the modulation depth is 0.9. It can be seen that the harmonics are mainly distributed around the sideband harmonics centred at 3 kHz. This shows that the equivalent switching frequency of the inverter output phase voltage is twice the carrier frequency, and the frequency doubling effect is achieved. Figure 14 is the transient process of the inverter start-up at a low modulation depth of 0.5. We can see that the phase voltage is always a three-level waveform, with the charging of the t(10ms/div)  clamping capacitor, the amplitude of the phase voltage u AO output level gradually decreases from 24 V. Until U C is 12 V, the amplitude of the u AO output level decreases to 12 V. In addition, during the U C charging process, the current i o waveform becomes smoother and approaches a sinusoidal waveform. It can be seen from Figure 15 that although the modulation depth is reduced to 0.5 and the output phase voltage u AO waveform is reduced to three levels, the U C is stable at 12 V and the output three-level waveform is stable. And under different loads, the voltage waveform u o across the resistor and the filtered current i o waveform also approached a sine wave. Comparing the current waveform during the transient state in Figure 14, it is very obvious that the current waveform after the steady state is closer to a sine wave. This is basically consistent with the simulation Figure 8, and it also fully illustrates that when the load characteristics are different at low modulation depth, the clamping capacitor can still achieve voltage selfbalancing.
It can be seen from Figure 16 that the harmonics are also mainly distributed near the sideband harmonics centred at 3 kHz, and the equivalent switching frequency of the inverter output phase voltage is twice the carrier frequency, which also achieves the frequency doubling effect.  Figure 17 shows the measured efficiency curve of this system. It can be seen that the efficiency of this system is above 90% under most modulation depth, and it can achieve over 95% efficiency at medium and high modulation range.
f (500Hz/div) u AO (20V/div) 2V/div In this paper, the topology output five-level requires only 7 devices, and there is only one capacitor. Compared with NPC and FC topologies, this system has great advantages in terms of device requirements and difficulty in balancing capacitor voltage. In terms of volume, the volume of this system is similar to the three-level NPC type and flying capacitor type topology. After adopting this topology, the existing three-level NPC type or flying capacitor medium-voltage transmission system can realize five-level output under the condition that the volume is basically unchanged, and a better output power quality can be obtained.

CONCLUSION
In this paper, a single-capacitor five-level inverter topology is described, which is a combination of a three-level topology and a half-bridge, compared with other five-level topologies, it has the advantages of fewer devices and smaller size. In order to control the clamping capacitor voltage in the topology, we propose an SPWM control strategy based on dual-modulated waves, which is easy to implement without a closed loop. The conclusions of simulation and experiment are as follows: 1. The SPWM control strategy based on double modulation wave achieves the voltage self-balancing of the capacitor by controlling the clamping capacitor to have the same charge and discharge time in each carrier cycle without adding additional circuits. 2. Experimental results at multiple modulation depth prove that the SPWM control strategy based on dual modulation waves is applicable at any modulation depth. From the spectrum analysis results, the SPWM control strategy based on the double modulation wave also improves the equivalent switching frequency of the inverter output voltage and achieves the frequency doubling effect.