A single‐stage AC‐AC solid‐state transformer with ZVS operation

Funding information National Natural Science Foundation of China, Grant/Award Numbers: 61873289, 61903381, 2019GK2211 Abstract Solid-state transformer (SST) is an attractive concept, which provides galvanic isolation and voltage scaling by means of a medium-frequency link. In this paper, a single-stage alternative current (AC)-AC SST solution without bulky energy storage elements is presented. The front-end rectifier (FER) and rear-end inverter (REI) of the SST works at line-frequency, while the intermediate LLC series resonant converter (SRC) fulfils the tasks of galvanic isolating and regulating the output voltage. To achieve high efficiency and bidirectional power flow capability of the SST, the zero voltage switching (ZVS) condition of the LLC SRC is comprehensively analysed, and the parameters design method of the LLC SRC is developed, where the resonant currents are constructed by applying the same gating signals to the primary-side and secondary-side bridges and the dead-time is properly selected. Consequently, the presented SST has the merits of high conversion efficiency, naturally bidirectional power flow capability, potentially high power density and high reliability. The experimental results on a 1.5 kW SST prototype show that sinusoidal input and output current, ZVS operation over the full load range are achieved, and the peak efficiency is 97.63%. The experimental results verify the functionality and effectiveness of the developed methods.


INTRODUCTION
Solid-state transformers (SSTs) have the potential to replace the conventional line-frequency transformer (LFT) in many applications, such as in electric traction, renewable energy systems, and smart distribution grids, due to the advantages of multi-functions, faults isolation and flexible connectivity [1][2][3][4][5][6][7][8]. However, issues like low efficiency, low power density, and poor reliability are still major challenges for its industrial applications, and most of the research works aim at addressing these issues.
In fact, the efficiency, power density and reliability features of SSTs depend greatly on the topology structure. Among the numerous presented SST topologies, the alternative current (AC)-direct current (DC)-AC topology is the most commonly used one due to its excellent controllability [9][10][11][12][13]. However, because of the multi-stage conversion structure and the bulky energy storage capacitors, the efficiency, power density and reliability performance of these AC-DC-AC SSTs may degrade. Compared with the AC-DC-AC SSTs, direct AC-AC SSTs are possible to achieve higher efficiency, higher power density and higher reliability due to fewer conversion stages and the absence of energy storage elements [1,[14][15][16][17][18][19][20][21][22].
In addition to topology structure, soft switching techniques, such as zero voltage switching (ZVS) and zero current switching (ZCS), are also effective measures to improve the efficiency of SSTs. The dual active bridge (DAB) converter has the advantage of good ZVS capability, which is usually adopted as the DC-DC stage of SSTs. However, the ZVS operation of DAB depends on loads and voltage conditions. Different from DAB, the LLC series resonant converter (SRC) has the merit of loadindependent ZVS operation and thus it is considered as an excellent solution for the DC-DC stage of the SSTs. In [22], a current-fed SRC-based SST with wide ZVS ranges is presented. However, bidirectional power flow and output voltage control schemes of the SST, which are of great importance in some applications such as power distribution network, are not involved in this work. In [23] and [24], a modulation scheme to achieve ZVS on both primary and secondary bridges of the SRC is proposed for the AC-DC SST, where a small phase shift between the gating signals of the primary and secondary bridges is introduced, to generate the tiny resonant current required by the ZVS operation of the secondary bridge during the deadtime.
Compared with the AC-DC SST, ZVS operation is more difficult to realize for the direct AC-AC SST, because the voltage across the MOSFETs is time-varying. Besides, there exist high frequency parasitic oscillations during the dead-time caused by the parasitic parameters, such as the output capacitors of the MOSFETs, stray capacitors of the power circuits. The effects of parasitic oscillations cannot be ignored on some occasions because ZVS operation may be affected, especially when the oscillation frequency is close coming to the resonant frequency [24]. In [25], an input-series-output-parallel direct AC-AC SST topology and theoretical analysis for power losses and circuit operation are presented. However, for direct AC-AC SST, considering the time-varying blocking voltage of the MOSFETs and the parasitic oscillations, ZVS condition analysis of a direct AC-AC SST is more complex than that of the AC-DC SST.
A single-stage AC-AC SST solution without bulky energy storage elements is presented here. The circuit operation modes and ZVS conditions of the LLC SRC considering parasitic circuit parameters are analysed in detail. The ZVS condition of the LLC is studied systematically, and the system parameters design method is developed to achieve ZVS and high conversion efficiency over wide load range conditions. A synchronous PWM modulation strategy is presented to realize naturally bidirectional power flow of the LLC without logical switching, and bidirectional power flow capability of the SST is verified experimentally. Besides, the closed-loop control of output voltage is presented to eliminate the effect of grid disturbances such as voltage sag, voltage swell and so on. Therefore, improved output voltage quality of the SST is achieved, which is of great significance for some applications such as power distribution network.
The remainder of this paper is organized as follows: Section II introduces the topology and operating principles of the single-stage AC-AC SST; Section III presents the analysis of operating behaviour and ZVS conditions followed by the design guidelines of the LLC SRC. In Section IV, the control scheme of the SST is developed to achieve a controllable output voltage. Section V shows the experimental results to verify the correctness of the presented methods. Section VI concludes this paper.

The AC-AC SST topology
The circuit diagram of the SST topology is shown in Figure 1 and it consists of a front-end rectifier (FER), a rear-end inverter (REI) and an LLC SRC, where the arrows represent the reference directions of currents. In this topology, both the FER and the REI act as line-commutated converters, whose switching states are only determined by the polarity of the input voltage. The LLC SRC consists of a medium frequency (MF) transformer, primary-side bridge, secondary-side bridge and a resonant tank, which provides galvanic isolation and output voltage regulation. The resonant tank of the LLC SRC is composed of a resonant inductor L r , a magnetizing inductor L m and a resonant capacitor C r . It should be noted that different from the bulky DC-link capacitors in the conventional SSTs, the capacitors C p and C s in this topology are small film capacitors used for filtering and commutating. Because there is only one LLC SRC stage that involves high frequency switching, the presented topology in this work is named as "single stage AC-AC SST".

Operating principles
For the single-stage SST, the FER and REI are commutated according to the polarity of input voltage. When the input voltage is positive, switches S 1 , S 4 of the FER and switches S 13 , S 16 of the REI are always on. Otherwise, switches S 2 , S 3 , S 14 and S 15 are turned on. As a result, the sinusoidal input voltage is converted into half-cycle sinusoidal primary-side DC-link voltage, while the half-cycle sinusoidal secondary-side DC-link voltage is transformed into a sinusoidal output voltage. To achieve ZVS of the primary-side bridge for the LLC SRC, the magnetizing inductance of the MF transformer is designed to generate large enough magnetizing current i m . Further to ensure ZVS operation of the secondary-side bridge, the gating signals of the secondary-side bridge are the same as that of the primary-side bridge, and the dead-time is specially chosen to construct the required secondary-side resonant current, which is different from the conventional LLC SRC. Figure 2 shows the magnified waveforms of the LLC SRC under forward power flow, where t d is the dead-time, i r and i s are the primaryside and secondary-side resonant currents, t 0 is the starting time of a switching cycle, t 1 and t 2 are the starting time and ending time of the dead-time.
It can be seen from Figure 2 that the phase of i s leads that of i r . This is because the magnetizing current i m is a fixed component irrelevant to the load condition and i r is decided mainly by i s . And i s is determined by the instantaneous output power of the SST. Therefore, when the polarity of the instantaneous output power is positive, i s leads i r . Otherwise, i r leads i s .
The key waveforms of the single-stage SST are shown in Fig    The key operating waveforms of the presented SST and u dc2 are the primary-side and secondary-side DC-link voltages, u o and i o are the output voltage and current, respectively. As shown in Figure 3, the DC-link voltages are the absolute values of the sinusoidal time-varying waveforms, which means that ZVS operation over the entire input voltage period is a challenge for the presented SST.

OPERATION MODES AND ZVS ANALYSIS OF THE SST
As analysed in Section II and shown in Figure 3, the FER and REI of the SST work at line-frequency, and thus operation modes of the FER and REI are not discussed here. In this section, only the LLC SRC of the SST is analysed in detail. During the dead-time, the resonant currents i r and i s oscillate due to the parasitic parameters. Therefore, by designing the system parameters and the dead-time properly, it is possible to utilize the oscillation to achieve ZVS operation by constructing the specific resonant currents in the dead-time.

Analysis of the operation modes of the LLC SRC
As shown in Figure 2, there are two modes within a half cycle of the resonant period, and the detailed analysis is given as follows.
Mode 1 [t 0 -t 1 ]: In this mode, the switches S 5 , S 8 , S 9 , S 12 are on and switches S 6 , S 7 , S 10 , S 11 are off. Before t 0 , the primary-side resonant current i r flows through the body diode of switches S 5 and S 8 , while the secondary-side resonant current i s flows through the body diode of switches S 9 and S 12 . Then, the output capacitors of switches S 5 , S 8 , S 9 , S 12 are discharged to zero voltage and switches S 5 , S 8 , S 9 , S 12 are turned on with zero voltage. During the time interval t 0 -t 1 , the primary-side resonant current i r flows through the switches S 5 , S 8 while the secondaryside resonant current i s flows through the switches S 9 and S 12 . The equivalent circuit in this mode is shown in Figure 4, where the resonant inductor L r and capacitor C r participate in the resonance operation. The input and output voltages of the MF transformer V AB and V CD are treated as two voltage sources, and the voltage across the magnetizing inductor is clamped by the secondary voltage V CD .
Mode 2 [t 1 -t 2 ]: In this mode, all switches of the LLC SRC are in the off state. At time t = t 1 , the switches S 5 , S 8 , S 9 , S 12 are turned off. The circuit composed by L r , L m , C r and the output capacitors of switches including C 5 , C 6 , C 7 , C 8 , C 9 , C 10 , C 11 , C 12 start to oscillate. The equivalent circuit in mode 2 is shown . During this interval, i r discharges C 6 , C 7 and charges C 5 , C 8 , i s discharges C 10 , C 11 and charges C 9 , C 12 , and the voltages across the switches S 6 , S 7 , S 10 , S 11 are zero at time t = t 2 , consequently, switches S 6 , S 7 , S 10 , S 11 are turned on with zero voltage.
As mentioned previously, the oscillation of i r is a key factor to achieve ZVS operation, because i r determines the boundary conditions of ZVS. To obtain the analytical expression of i r , mathematical models of the LLC SRC with different modes are deduced as follows.
In mode 1, the mathematical model of the resonant tank is written as: where v cr is the voltage across the resonant capacitor C r . According to Equations (1)-(3), i r is derived as: In mode 2, the output capacitors of the switches, C r , L r and L m participate in the resonance process, where the mathemati-cal model of the LLC SRC is expressed as: are the voltages across the capacitors C 5 , C 6 , C 7 , C 8 , C 9 , C 10 , C 11 , C 12 , respectively.
Equations (1, 2) and (3) are also valid for mode 2. The output capacitor of the switch is non-linear, and the capacitance of the output capacitor increases with the decrease of the voltage across the switch. Therefore, for the single-stage SST, it is difficult to realize ZVS near the zero cross point of the input voltage. Despite all this, the switching losses of the switch near the zero cross point of input voltage can be ignored because both the voltage across switch and the resonant current are very small. To simplify the theoretical analysis, we assume that the capacitance of the output capacitor of the switches is identical and the capacitance is C oss , i r1 = i r2 and i s1 = i s2 . Then Equation (1) can be deduced as: According to Equations (5) and (6), the resonant capacitor voltage is written as: Substituting Equations (3) and (8) into Equation (7), the relationship between the currents i r and i s is given as: Combining Equations (2) and (5), the second-order differential model of the MF transformer is: Then, the fourth-order differential model of i r is calculated by Equations (9) and (10) as, According to Equation (11), the general solution of i r can be derived as and ω rs and ω rs ′ are expressed as: where =L m L r n 2 C oss , = L m n 2 (C oss ∕C r + 1) + L m + L r , and = 1∕C r + 1∕C oss . According to Equations (1), (5) and (9), the first to third order differential models of i r are deduced as: (15) and (12), the specific solution of i r is solved as:

Analysis of the ZVS conditions
To fulfil ZVS condition of the primary-side bridge, the primaryside resonant current direction should remain unchanged during the dead-time, to ensure full discharge of the output capacitors of the switches before turn-on. Similarly, to achieve ZVS operation of the secondary-side bridge, the direction of the The upper limit of the dead-time versus system parameters (a) C r and C oss , for L r = 6.8 μH, L m = 90 μH; (b) L r and L m , for C r = 0.9 μF, C oss = 1 nF secondary-side current should also remain unchanged during the dead-time. Therefore, half of the resonant current oscillation period should be longer than the dead-time, which is t d < π/ω rs . From Equation (13), the upper limit of the deadtime is calculated as: The upper limit of the dead-time versus different system parameters is plotted in Figure 6. As shown in Figure 6, the oscillation frequency is not sensitive to the resonant capacitor C r and the magnetizing inductor L m while it is sensitive to the resonant inductor L r and the output capacitor C oss . The oscillation frequency increases with the decrease of L r and C oss .
To realize the ZVS operation of the primary-side bridge, the output capacitor of the switches should be fully discharged, and its condition is expressed as: where C strayp is the lumped stray capacitor across the primaryside resonant tank, U im is the amplitude of the input voltage, Q ossp is the charge of the output capacitor of the primary-side switch and it is expressed as: where k a and k b are the specific parameters associated with the switches. Equation (18) can be further deduced as: It should be noted that the capacitance of the output capacitor depends on the voltage across the switch. However, Equation (17) is still valid for non-linear capacitance. In fact, to achieve ZVS we only need to ensure that the direction of the resonant current does not change and the output capacitors are fully discharged during the dead-time.
Similarly, for the secondary-side bridge, the ZVS condition is given as: where Q osse is the charge of the output capacitor of the secondary-side switch and C strayse is the lumped stray capacitor across the secondary-side circuit; U om is the amplitude of the output voltage of the SST. Because the dead-time is small, the magnetizing current i m is considered constant during the dead-time. Then, the secondaryside ZVS condition is given as: And the secondary-side ZVS condition can be derived further as: In this case, once the SST system parameters are given, ZVS is achieved when Equations (17), (20) and (23) are satisfied.

System parameters designing
In all, the design guideline of the LLC SRC is given as follows. The first step is to determine the switching frequency, because the switching frequency is vital to the performance of the LLC SRC. Although a low frequency helps to decrease the switching losses of the converter, it results in a large volume of the transformer and capacitors. A high frequency is beneficial to improve the power density of LLC SRC, but it leads to large losses of the power conductors and the transformer's magnetic core and increases the system EMI concerns. Then, according to the switching frequency and the rated resonant current, the resonant inductor and resonant capacitor could be selected. The resonant inductor affects the amplitude of the resonant current and the resonant capacitor is constraint by the voltage across it. As shown in Figure 6, the upper limit of the dead-time is sensitive to the resonant inductor, thus it should also be taken into consideration. Finally, to achieve ZVS operation, the magnetizing inductor and dead-time are designed according to Equations (17), (20) and (23). As shown in Equations (20) and (23), the ZVS constraint is determined by the resonant current and the dead-time, while the dead-time is constraint by the magnetizing inductor. When the magnetizing inductor is close to the resonant inductor, it will affect the upper limit of the dead-time dramatically. The design guidelines for the DC link capacitors C p and C s are discussed as follows.
For the discussed topology in this work, the upper limit of the capacitance of the DC-link capacitor C p and C s is mainly determined by the expected input power factor: where , P in , ω in and V in(RMS) are the rated input power factor angle, the rated input active power, angular frequency of the input voltage and the rated input RMS voltage, respectively. On the other hand, the lower limit of the capacitance of the DC-link capacitors is determined by the allowable voltage ripples across C p and C s . As can be seen from Figure 1, during the positive half cycle of the input voltage, the current of C p can be written as: where I im is the amplitude of input current. The voltage ripple of C p can be solved by integrating the capacitor current And the voltage ripple can be deduced further as: Define the voltage ripple coefficient as where ω in is the input voltage frequency, f s is the switching frequency of LLC resonant converter. Then, the lower capacitance limit of C p is expressed as: For the secondary-side DC link capacitor C s , the lower limit of the capacitance can be solved in a similar way.
In this work, with the constraints of the rated input power factor ≥ 0.99 and the capacitor voltage ripple coefficient ≤ 10%, the primary-side DC link capacitor C p and the secondary-side DC link capacitor C s are both selected as 3.3 μF.
As can be seen from the above design guideline for the DC link capacitors, the capacitance of the DC link capacitors is close to that of the resonant capacitor. Therefore, the influence of the DC link capacitors on the resonant frequency should be examined carefully. Based on the time domain analysis tool, the analysis of the influence of the DC link capacitors on the resonant process is given as follow.
To solve the resonant current i r , the time domain equation can be derived as: The analytical solution of resonant current can be derived as: ; I r , and T rep represent the magnitude, initial phase and actual resonant period of the resonant current i r .
To solve the initial phase , the equation of resonant current zero-cross point is written as: According to the Equation (33), the current i i can be expressed as: Besides, the resonant capacitor voltage amplitude can be derived by power balance where f re is the actual resonant frequency. The resonant capacitor voltage amplitude can also be solved by integrating the resonant current (35) and (36), the following equation can be obtained: According to Equations (33) and (37), the initial phase can be derived as: For the designed system parameters in this work, the initial phase is solved as = 0.227. Therefore, the actual resonant frequency f re can be calculated as: which is a bit higher than the ideal resonant frequency f r defined by: where f n is the normalized frequency and f n = f s /f r , f s is the switching frequency; L n = L m /L r is the normalized inductance, Q s is the quality factor of the LLC SRC and Q s = √ L r ∕C r ∕R L , R L is the equivalent load resistor of the LLC SRC.

OUTPUT VOLTAGE REGULATION OF THE SST
According to Equation (41), the voltage transfer gain is determined by Q s , L n and f n , and the output voltage of LLC can be regulated by changing the switching frequency.
Then, the voltage control scheme based on the conventional frequency-domain method is developed as shown in Figure 7, where u dc2 * is in phase with u dc1 and its amplitude is the same as the desired AC output voltage, LLC SRC tracks the reference voltage u dc2 * by adjusting the switching frequency. For the target of a 500 Hz bandwidth and a 0.707 damping ratio for the control system, the discrete voltage feedback compensation is designed as: with a control frequency of 20 kHz.
When the system parameters are settled, the range of frequency control is restricted by the resonant frequency, and L n is determined by the magnetizing inductance. According to Equation (24), to meet the requirements of ZVS operation, the normalized inductance L n is selected as 12, and the voltage gain versus the normalized frequency is shown in Figure 8. To meet the regulation demand and maintain the switching frequency within the proper range, the normalized frequency is designed as 0.8-1.2. As has been presented in [28], the LLC converter becomes a LC SRC when it runs in reverse power flow direction, and the mode and voltage transfer function are different from that of the forward case. Though the output voltage control framework in Figure 7 is valid for both the forward and reverse power flow directions, the switching frequency range as well as the controller parameters in reverse power flow should be redesigned [27]. For simplicity the detailed analysis and design for the reverse power flow case are not elaborated here.
In essence, the magnitude of the fundamental component of the resonant converter that determines the secondary-side DC link voltage, is the only control objective from the perspective of the first harmonic approximation (FHA) theory. Since the secondary-side DC link voltage pulsates at twice the line frequency (100 Hz), a 20 kHz control frequency is sufficient to achieve good control performance of the secondaryside DC link voltage as well as the output voltage of the SST.

EXPERIMENTAL RESULTS
To validate the correctness of the presented methods, a 1.5 kW prototype with the system parameters shown in Table I is built, as shown in Figure 9. The switches of the FER and REI are 600 V/72 mΩ MOSFETs (FCH072N60F) due to its low conduction losses, and the control platform is DSP TMS320F28069.  The total harmonic distortion of the input current and output voltage are 0.57% and 0.28%, respectively. To demonstrate the bidirectional power flow capability of the SST, an external grid connected single phase inverter is selected as the load of the SST in the next tests, and the output power, as well as the power flow direction of the SST are changed by setting the active and reactive components of the grid-connected current of the external grid-connected inverter. And in the whole tests the output of the SST is controlled as a voltage source. Figure 11 shows the waveforms of the SST with the external grid-connected inverter load, where the input power factor of the external grid-connected inverter is non-unity and the power flow direction of the SST is forward. As shown in Figure 11, the output voltage still tracks the desired AC output voltage well, and the input current of the SST is sinusoidal but is not in phase with the input voltage. This is because of the uncontrollability of the FER, the input current of the SST is indirectly synthesized by the output current and thus the phase angle of the input current is the same as that of the output current.  Figure 12 shows the waveforms of the SST under reverse power flow direction, where a pure minus active component of the desired grid-connected current is set for the external gridconnected inverter. As shown in Figure 12, the output voltage and input current are still sinusoidal, and the input current is out of the phase with the input voltage, demonstrating the reverse power flow of the SST. Therefore, sinusoidal input current and output voltage, and bidirectional power flow capability are achieved in the SST. Besides, it can be seen that the input and output current quality of the SST in Figure 12 is poorer than that in Figure 10. This is because when the external grid connected inverter is used as the load, the output current of the SST (also the input current of the external grid connected inverter) contains high frequency harmonic components generated by the external grid connected inverter. Therefore, the input and output current quality of the SST when feeding the  external grid connected inverter is inferior to that of the resistor load inevitably. Figures. 13 and 14 show the waveforms of the LLC SRC under 1 and 1.5 kW load, respectively, where u dsp and u gsp are the drain to source voltage and gate to source voltage of the primary-side; u dss and u gss are the drain to source voltage and gate to source voltage of the secondary-side. As shown in Figure 13(a,c), the DC-link voltage is shaped as the absolute value of the sinusoid waveform, and the envelope of the resonant current is in phase with the input voltage. From Figure 13(c) and Figure 14(c), both the falling edge of the drain-to-source voltage of the primary-side and the secondary-side MOSFETs precede the rising edge of gate-to-source voltage of the MOSFETs. For the presented SST, because the primary-side DC-link voltage varies from 0 to 311 V in a line cycle, these results demonstrate that ZVS operation of LLC SRC is achieved in wide input voltage and load ranges. Figure 15 shows the output voltage regulation capability of the SST. Figure 15(a) shows the input and output waveforms when the input voltage drops to 0.9 times of the rated value.

Experiments
For the conditions of the input voltage rising to 1.1 times of the rated value, Figure 15(b) shows the results of input and output waveforms. As can be seen from Figure 15, the output voltage achieves the rated value of 220 V rms with the developed output voltage control method, which demonstrates the effectiveness of the output voltage control method.

Efficiency evaluation
In this part, first, the power losses and system efficiency are calculated. Then the practical efficiency of the prototype is measured by a HIOKI 3390 power analyser and is compared with the calculated one and the matrix-type SST discussed in [21].
Since the FER and REI are commutated at line frequency, the power losses are mainly the conduction losses. The total power losses of the FER and REI, denoted as P lossp , is expressed as: P lossp = (2I i 2 + 2I o 2 )R on + P lossL (42) where P lossL is the losses of input filter inductor calculated as P lossL = I 2 i R cui + P coreloss , R cui is the resistance of the input filter inductor and P coreloss is the core loss of input filter inductor; I i and I o are the input and output RMS currents, respectively; R on is the on-state resistance of the switches of the FER and REI.
For the LLC SRC, since ZVS is achieved for both sides and the turn-off currents of the LLC SRC are small, the power losses of the LLC SRC are mainly the conduction losses which are calculated as: where R on-p and R on-s are the on-state resistance of the primaryside and secondary-side bridge switches, respectively; I r and I s are the primary-side and secondary-side resonant RMS currents, respectively; P losst is the total loss of MF and the resonant capacitor. Thus, the efficiency of the presented SST prototype is, where P aux is the power provided by the auxiliary power supply. Figure 16 shows the comparative results of the calculated and measured efficiencies and the efficiency of the matrix-type SST in [21].
As shown in Figure 16, because of the lower switching losses of the inversion stage, the efficiency of the presented AC-AC SST is obviously higher than that of the work presented in [21]. Furthermore, it can be seen that the measured efficiencies are in good agreement with the calculated ones, and the measured peak efficiency is 97.63%; the efficiency of the actual prototype under rated load condition is measured as 96.21%. It is satisfactory for a small power rating AC-AC SST.

CONCLUSION
In this paper, the ZVS conditions and design guidelines of the single-stage AC-AC SST solution without bulky energy storage elements are analysed comprehensively. By applying the same gating signals to the switches of the primary and secondary sides and designing the system parameters properly, natural bidirectional power flow capability and ZVS operation over wide input voltage and load ranges are achieved. The presented closed-loop control of the output voltage can eliminate the effect of grid disturbances. As a result, high output voltage quality of the SST is achieved. The experimental results verify the effectiveness of the presented methods, and the peak efficiency reaches 97.63%. Due to its advantages such as high conversion efficiency, natural bidirectional power flow capability, controllable output voltage, high power density, and improved output voltage quality, the AC-AC SST is an attractive candidate for many applications such as power distribution network.