Analysis and improvement of fourth-order generalised integrator based phase-locked loop

The fourth-order generalised integrator is very suitable for single-phase phase-locked loop because it can provide orthogonal signal conveniently and block harmonic voltages effec-tively. In the conventional fourth-order generalised integrator based phase-locked loop, the resonance frequency of fourth-order generalised integrator needs to be adjusted according to the grid frequency. To improve the phase-locked loop performance, a non-adaptive fourth-order generalised integrator is suggested for single-phase system, and this paper presents a correction method. According to the estimated grid frequency, the amplitude imbalance and phase error caused by non-adaptive fourth-order generalised integrator can be calculated, and two adaptive units are added to deal with the problems. Moreover, the small-signal model of the proposed phase-locked loop is carried out, and the control parameters are tuned. Compared to conventional fourth-order generalised integrator based phase-locked loop, the proposed phase-locked loop shows a better performance, which is veriﬁed through simulation and experimental results.

system, the aforementioned prefilters cannot be applied directly, and a QSG is required for generating orthogonal signal. In the DT-based QSG, differential term even amplifies high-order harmonics. With obvious advantages, SOGI not only provides fictitious quadrature signal but also acts as a prefilter and exhibits a significant rejection capability for high-order harmonics [20].
Voltage signal often contains DC offset, which may be caused by a half wave rectifier, measurement devices, grid faults, etc. [28][29][30]. The DC offset will be converted to the fundamental frequency disturbance in the dq-frame, which is difficult to block due to its low frequency [30]. The SOGI is a single-input and dual-output structure. Its in-phase (α-axis) channel acts as a band-pass filter and can reject DC offset. Unfortunately, its quadrature-phase (β-axis) channel acts as a low-pass filter and is sensitive to DC offset [19,20]. Many methods have been carried out to enhance its harmonic rejection capability of DC offset and low-order harmonics. In [31], a third-order generalised integrator (TOGI) is suggested. The TOGI exhibits a stronger disturbance rejection capability for some low-order harmonics, but is still sensitive to DC offset. In [19], a strategy is suggested to modify the SOGI against DC offset, but it cannot enhance the harmonic rejection capability for most low-order harmonics. In [32], the structure of multiple SOGIs (MSOGI) is presented. The low-order harmonics are extracted through multiple parallel SOGIs and then eliminated by a harmonic decoupling network (HDN). Nevertheless, the MSOGI leads to much computational burden and its harmonic rejection capability cannot be improved significantly. Recently, a fourth-order generalised integrator (FOGI) is suggested in [20], which can block DC offset in both the in-phase and quadrature-phase channels, and exhibits a stronger disturbance rejection capability than the SOGI.
In the conventional FOGI-based PLL (FOGI-PLL), an adaptive FOGI (AFOGI) is used, and its resonance angular frequency is updated according to the estimated grid frequency. When the grid voltage is at off-nominal frequencies, the FOGI-PLL can output accuracy phase. If a non-adaptive FOGI (NFOGI) is used, the PLL will suffer from amplitude imbalance and phase error. To deal with these problems, two correction units are added to the proposed PLL. Compared with conventional FOGI-PLL, the proposed PLL shows a better performance. This paper is organised as follows. Section 2 provides an analysis of the conventional FOGI-PLL. In Section 3, the amplitude imbalance and phase error caused by NFOGI are analysed and corrected. In addition, this section presents the smallsignal models of the conventional FOGI-PLL and the proposed PLL. Sections 4 and 5 provide the simulation and experimental results, respectively. Section 6 concludes this paper.

ANALYSIS OF FOGI-PLL
The transfer function of standard second-order system (SOS) can be expressed as [20] S (s) = 2 u where ω u and ζ are the damping factor and undamped natural angular frequency, respectively. According to (1), Figure 1 shows a structure for implementing the SOS, where K 1 = ω u /(2ζ) and K 2 = 2ζω u , and v and v α are the input and output signals, respectively.
The structure of FOGI can be obtained by replacing the integrators in Figure 1 with generalised integrators [33] and adding an output channel. Figure 2 shows the structure of FOGI, where ω, v, v α and v β are the resonance angular frequency, input signal, in-phase and quadrature-phase output signals, respectively [20].
According to Figure 2, the transfer functions of FOGI can be obtained as [20] where G α (s) and G β (s) are the transfer functions of in-phase and quadrature-phase channels, respectively. Obviously, both G α (s) and G β (s) are fourth-order functions. The FOGI is also called second-order SOGI (SO-SOGI) because it is derived from the SOS. Its response time can be tuned by adjusting the gains k 1 and k 2 . In [20], k 1 = 1.56 and k 2 = 3.11 are recommended for FOGI, and the corresponding damping factor ζ is equal to √2/2. It should be noted that the parameters of FOGI are tuned according to the SOS [20]. Figure 3 shows the amplitude-and phase-frequency plots of FOGI. This paper considers the nominal frequency f n = 50 Hz and nominal angular frequency ω n = 2π × 50 rad/s. It can be observed that the phase-frequency response of in-phase channel G α (s) is 90 • ahead of that of the quadrature-phase channel G β (s) at all frequencies, that is, the output signals v α and v β keep orthogonal always [20]. Figure 4 shows the general structure of OSG-based PLL [15,34,35]. By replacing the QSG with FOGI, the  The general structure of QSG-PLL structure of conventional FOGI-PLL can be obtained, as shown in Figure 5, wherêg and̂are the estimated grid angular frequency and phase, respectively. In this structure, the FOGI acts as a QSG and disturbance rejection filter at the same time. To obtain an accurate voltage phase, the resonance angular frequency of FOGI is updated according to the estimated angular frequency in Figure 5. An amplitude normalisation scheme (ANS) is included, which makes the PLL insensitive to the voltage amplitude variation. Here, the method of ANS is dividing the signalv q by the square root ofv q andv d [3,7]. Figure 6 shows the structure of NFOGI-based PLL (NFOGI-PLL), where the resonance angular frequency of NFOGI is fixed at the nominal angular frequency. At nominal frequency, the in-phase channel of NFOGI provides unit amplitude and 0 • phase gain, and the quadrature-phase channel provides unit

THE PROPOSED TECHNIQUE
The structure of conventional FOGI-PLL

FIGURE 6
The structure of NFOGI-PLL

FIGURE 7
Performance of the NFOGI-PLL under +2 Hz frequency step change amplitude and −90 • phase gain, which can be observed from Figure 3. Therefore, the NFOGI-PLL can output the accuracy phase of the FFC at nominal frequency. Unfortunately, the NFOGI-PLL suffers from amplitude imbalance and phase errors at off-nominal frequencies.
In [17], the non-adaptive SOGI (NSOGI) is recommended, but the structure of NFOGI is more complex than NSOGI. In this section, the correction method for NFOGI-PLL is proposed.

Correction of amplitude imbalance
According to Figure 3, the amplitudes of in-phase and quadrature-phase output signals are not equal at off-nominal frequencies. The amplitude imbalance of v α and v β will lead to a disturbance signal in the control loop. Therefore, the NFOGI-PLL will suffer from oscillatory errors, which can be observed from Figure 7. Note that the phase error θ err is equal to the difference between the estimated phasêof the PLL and the phase θ 1 + of the FFC, that is, err =̂− + 1 . To correct the amplitude imbalance, we need to analysis the amplitude-frequency response of the NFOGI.

FIGURE 8
The structure of NFOGI-PLL with an amplitude corrector

FIGURE 9
Performance of the PLL in Figure 8 where ω g is the grid angular frequency. According to (3) and (4), the amplitude relationship of the NFOGI output signals can be obtained as To correct the amplitude imbalance, the quadrature-phase output signal v β can be multiplied bŷg∕ n . Figure 8 shows the structure of the NFOGI-PLL with an amplitude corrector, where k a =̂g∕ n . When the grid frequency is equal to the nominal value, k a is equal to 1. Figure 9 shows the performance of the PLL in Figure 8. The oscillation error is eliminated, but this structure still suffers from phase error at off-nominal frequencies. Next, this phase error will be analysed and corrected.

Correction of phase error
According to (3) and (4), the phase-frequency response of the in-phase and quadrature-phase channels can be obtained as Because the output signals of NFOGI are always orthogonal, we just need to analyse the phase error of one channel. Here, the in-phase channel is selected.

FIGURE 10
The phase-frequency response of the in-phase channel

FIGURE 11
The phase error δ between (6) and (8) According to the standard EN50160 [36], the lower and upper limits of grid frequency are 2π × 47 and 2π × 52 rad/s, respectively. Figure 10 shows the phase-frequency response of the in-phase channel in the allowable frequency range. For example, if the grid frequency is equal to 48 Hz, the phase ∠G is around 3 • .
Because the fluctuation range of grid frequency is very limited around the nominal value [36], (6) can be simplified as The simplified Equation (8) does not require trigonometric function, which can reduce the computational burden.
The phase error between (6) and (8) can be expressed as Within the allowable frequency range of the standard EN50160, the value of phase error δ is shown in Figure 11. The range of phase error δ is (−0.00960 • , 0.00244 • ), which confirms the accuracy of the simplified Equation (8). When the grid frequency is equal to the nominal value, the phase error δ is equal to 0. The output phase error of the PLL in Figure 8 is equal to ∠G . To correct this error, a simple method is to add ∠G to the output phasêof the PLL. Figure 12 shows the proposed structure, which this paper calls the improved FOGI-PLL (IFOGI-PLL). In this structure, k̂g = −∠G , and g and̂care the estimated angular frequency and phase, respectively, and the amplitude imbalance and the phase error of NFOGI-PLL are corrected. When the grid frequency is equal to the nominal value, the output of the phase corrector is equal to zero. Figure 13 shows the performance of the proposed IFOGI-PLL.

Small-signal model and control parameters design
In the SRF-PLL, the q-axis voltage v q is often used to measure phase [3]. Figure 14 shows the small-signal model of conventional SRF-PLL [3,37]. When an ANS is included in the SRF-PLL, the amplitude of FFC corresponds to 1 and does not appear in the model.
In what follows, we will analysis the influence of FOGI on the small-signal model of SRF-PLL. As mentioned in Section 2,  Figure 8 and FOGI-PLL not only is the FOGI derived from the SOS but also its parameters are tuned according to the SOS [20]. This paper adopts a similar modelling method. Assume that a sinusoidal voltage v (t) = V 1 + sin(ω g t +ϕ) is the input signal, where ω g and ϕ are the angular frequency and initial phase, respectively. The sinusoidal response of the FOGI can be expressed as [29,38,39] where H 1 , H 2 and ϕ' are the functions of V 1 + , ω g , ϕ, ζ and ω n . Their detailed expressions are not shown here because they do not affect subsequent derivation. When ω g is equal to ω n , H 1 and ϕ' are equal to V 1 + and ϕ, respectively. The second terms on the right-hand side of (10) decays to 0 in steady state, and the decaying time constant is equal to ζω n . Because ζ and ω n are the  To obtain the small-signal model, the dynamics of FOGI should be transferred to the dq-frame. In the frequency domain, the transformation from the αβ-frame to the dq-frame corresponds to a frequency shift [27]. Under a quasi-locked state (the estimated frequency and phase of the PLL are closed or equal to the actual grid frequency and phase, respectively), the fundamental-frequency signal in the αβ-frame corresponds to a DC signal in the dq-frame. Therefore, the sinusoidal response of fundamental-frequency signal in the αβ-frame corresponds to a step response in the dq-frame.
To simplify the derivation, a first-order system (FOS) is used to approximate the FOGI in the dq-frame. The transfer function The step response of the FOS can be expressed as [38,39] where V DC is the amplitude of the step signal. According to (12), the decaying time constant of FOS is equal to k. When the same decaying time constant is selected for the FOS and FOGI, the coefficient k can be obtained as According to Figure 8, under a quasi-locked state, v q can be approximately expressed as In Figure 8, an ANS is included in the SRF-PLL, therefore, the amplitude V 1 + corresponds to 1, and v q can be expressed as According to (15), Figure 15 shows the small-signal model of the PLL in Figure 8.
According to Figure 15, the closed-loop transfer function of the PLL in Figure 8 can be obtained as (2) the frequency fluctuation is less than 0.2 Hz. b Here, the phase error and frequency error represent the peak error of the PLLs 1 min after the disturbance injection.

FIGURE 20 Experimental set-up
The parameter design of the prefilter-based PLL has been analysed in [30]. Since the denominator of the second term of Equation (16) is a SOS, the damping factor ζ a = √2/2 and natural angular frequency ω na = 2π × 20 rad/s are selected, and the corresponding parameters of the proportional-integral (PI) controller can be obtained as { k p = 177.71 Similar to [3,40,41], the estimated angular frequency can be assumed as a constant (equal to the nominal angular frequency ω n ) in the derivation process of small-signal model of the adaptive filter-based PLL since the fluctuation range of grid frequency is limited around the nominal value. Within the allowable frequency range of the standard EN50160, the small-signal models of the PLL in Figure 8 and FOGI-PLL can be consid- ered the same, and therefore both PLLs can use the same control parameters.
Define ω g = ω n + Δω g , where Δω g denotes the deviation of the grid angular frequency ω g from the nominal value. According to (8), the phase corrector can be approximated as According to Figure 15 and Equation (18), Figure 16 shows the small-signal model of IFOGI-PLL, where k ε = −2/(k 1 ω n ).
According to Figure 16, the closed-loop transfer function of the IFOGI-PLL can be obtained as The denominators of the second term of Equations (16) and (19) are same, and therefore the IFOGI-PLL can use the control parameters in (17). After adding the phase cor- rector, the same control parameters can still be used, which may confuse some readers. To make it easier to understand, an intuitive perspective is provided here. Observing Figure 16, note that the phase corrector does not affect the system stability, because it is outside the feedback loop. If the PLL in Figure 8 is stable, the proposed PLL in Figure 12 is also stable. Therefore, the same control parameters can be selected in the PLLs.

SIMULATION VERIFICATION
In this section, the HT-PLL [10], SOGI-PLL [15], FOGI-PLL and the proposed IFOGI-PLL are compared through simulation results. Compared with FOGI, the HT [10] is more complex, but the SOGI [15] is simpler. The results are carried out in the MATLAB/Simulink environment. The sampling frequency is fixed at 10 kHz. The nominal grid frequency is selected as 50 Hz, and the amplitude of the FFC is set as 1.0 pu. The same control parameters are selected for all PLLs.
To compare the performance conveniently, it is considered that a PLL settles to a steady state when the following conditions are satisfied simultaneously: the phase fluctuation is less than 0.5 • , and the frequency fluctuation is less than 0.2 Hz.
Here, three simulations are considered. Case 1: The grid frequency is fixed at 49 Hz. At 0.02 s, a +20 • phase jump occurs.
Case 2: The initial grid frequency is 50 Hz. At 0.02 s, a −2 Hz frequency step change and voltage sag (0.9 pu) occurs.
Case 3: The grid frequency is fixed at 51 Hz. At 0.02 s, a DC offset (0.08 pu) is injected. To further verify the robustness of all PLLs, the 5th, 7th, 9th and 11th harmonics are injected at the same time, and their amplitudes are all equal to 0.05 pu.
Simulation results in response to Cases 1, 2 and 3 are shown in Figures 17, 18 and 19, respectively. In all tests, the proposed IFOGI-PLL exhibits the shortest settling times and smallest overshoots. In Cases 1 and 2, no harmonic voltage is injected, and therefore the steady-state phase and frequency errors of all PLLs are equal to zero. In Case 3, the steady-state phase and frequency errors of the IFOGI-PLL and FOGI-PLL are equal and small, and SOGI-PLL and HT-PLL suffer from large oscillatory errors and are considered unstable.
Details of the simulation results are listed in Table 1. It can be observed that the IFOGI-PLL exhibits the best performance in these tests.

EXPERIMENTAL VERIFICATION
The experiments results are presented in this section. Figure 20 shows the experimental set-up. Two Texas Instruments TMS320F28335 digital signal processors (DSPs) are used to obtain the experimental results. The voltage signals are generated by the digital-to-analog converter of DSP A. DSP B receives voltage signals through an analog-to-digital converter, and is responsible for implementing the PLL algorithms at the same time. The sampling frequency is set as 10 kHz.
Here, four experimental tests are considered. Case 4: In this test, the grid frequency is fixed at 50 Hz, and a +30 • phase jump and voltage sag (0.7 pu) is triggered at the same time.
Case 5: The grid frequency is fixed at 50 Hz, and a −10 • phase jump occurs. To further verify the robustness of PLLs, a 0.5 Hz sub-harmonic, and the 6th and 12th harmonics are injected at the same time, and their amplitudes are all equal to 0.06 pu.
Case 6: The initial grid frequency is 48 Hz, and then grid voltage experiences +4 Hz frequency step change. A DC offset, the 7th harmonic, and two inter-harmonics (13.3th and 17.6th) are also injected, and their amplitudes are all equal to 0.1 pu.
Case 7: The initial grid frequency is 50 Hz. The grid voltage suffers −3 Hz frequency step change. To further verify the robustness of four PLLs, a sub-harmonic and all odd harmonics between 5th and 50th (i.e. 5 < h < 50) are injected, and their amplitudes are all equal to 0.05 pu. Figure 21 shows the performances of all PLLs in response to Case 4. The proposed IFOGI-PLL exhibits the shortest settling times and smallest overshoots.
Experimental results in response to Case 5, 6 and 7 are shown in Figures 22, 23 and 24, respectively. In these tests, the SOGI-PLL and HT-PLL are unstable after the disturbance injection. The steady-state phase and frequency errors of the IFOGI-PLL and FOGI-PLL are equal. Although the IFOGI-PLL and FOGI-PLL suffer from oscillation, they are significantly smaller than SOGI-PLL and HT-PLL, and exhibit better steady-state performance.
The detailed information of all experimental results is listed in Table 2. It can be observed that the IFOGI-PLL experiences shorter settling times than FOGI-PLL in these tests.

CONCLUSION
The FOGI is a recently proposed advanced technique for creating a fictitious quadrature signal and blocking harmonic voltage. To achieve a good performance, this paper suggested the NFOGI for single-phase PLL. Two adaptive correction units are added to the PLL, which are responsible for correcting the amplitude imbalance and phase error, respectively. When the grid is at the nominal frequency, the outputs of the amplitude and phase corrector are equal to 1 and zero, respectively. The correction units and small-signal model of the proposed PLL are described in detail. The simulation and experimental results demonstrate the superior performance of the proposed technique.