A new enhanced-boost switched-capacitor quasi Z-source network

This paper proposes a new enhanced-boost non-transformer-based impedance source network. The strong boosting ability of the proposed topology is realized by making use of the switched capacitor concept in the formerly introduced enhanced-boost quasi Z-source network (EB-qZSN) without any additional active switch. Meanwhile, the advantages of the EB-qZSN such as input current continuity and shared ground between the input and the output are maintained. In addition to the lower shoot-through requirement to obtain high voltage gains, the proposed impedance network takes advantage of a smaller size of passive components along with a lower input current ripple to achieve higher power density and higher efﬁciency. Moreover, the lower total rating of the switching elements, deﬁned by switching device power, directly translates to lower cost for the proposed method. The operation principles and the design guideline of components are explained in detail and a thorough comparison with other ZSN is presented. A 240W DC–DC prototype converter was built to validate the performance principles and properties of the proposed impedance network.

output waveform quality is obtained because there is no need for dead time. Due to these interesting features, many research works are intended for applying the ZSNs to DC-AC power conversion applications with novel control algorithms and modulation schemes [3][4][5]. They are also adopted to DC-DC [6][7][8], AC-DC [9] and AC-AC [10] power converters. The flexibility of ZSNs for employing in many types of power converters is investigated in [11]. Despite the advantages, the conventional ZSN suffers from serious drawbacks which restrict its practical applications. Besides a low voltage gain, discontinuous input current and lack of a joint ground between the input and the H-bridge inverter can be mentioned as the main limitations of the conventional ZSN. It can be greatly improved by modifying the component arrangements, which is introduced as quasi ZSN (qZSN) [12]. However, it has the same small gain as the conventional ZSN, which is a major problem particularly in renewable energy systems requiring a wide range of voltage gains. The need for high ST intervals in a ZSN, which has a low input-to-output gain ratio yields high voltage stress on semiconductors of the H-bridge inverter, a low modulation index followed by a low output voltage quality and a reduced efficiency.
Various ZSN topologies have been put forward in literature with high voltage boost factors. The switched inductor (SL) is a well-known technique to augment the voltage gain of the conventional ZSN and the qZSN. By replacing the inductors in these structures with SL cells, the SL-(q)ZSNs are realized [13], [14]. To further enlarge the boost capability, a novel SL-qZSN is proposed in [15], which utilizes the voltage-lifting unit in its structure. The extended-boost ZSNs proposed in [16], extend the output voltage gain range of the qZSN with extra passive components and diodes, which are arranged in two general manners called the capacitor/diode assisted ZSNs. The (quasi) switched boost networks (q)SBNs proposed in [17] and [18], offer the same voltage gain as that of the conventional ZSN in such a way that one LC pair is saved, although one additional active switch and one extra diode are used in these circuits. By integration of SLs in the SBN-based structures, higher boost factors can be obtained [19], [20]. Besides the high ripple of input current, circuit elements are faced with high voltage stresses in these structures. Further advancements in the SBN structures to achieve higher voltage gains are provided in [21] and [22], but there is no common ground between the input and the output. Another high-boost SBN-based structure is introduced in [23], which uses a low number of passive elements and diodes. However, the inconvenience of no common ground between the input and the output remains unsolved. In [24][25][26], the concept of the switched capacitor (SC) is used to realize a high voltage gain, but with the aid of an extra active switch. Another approach to realize a high-boost ZSN is to make use of coupled inductors [27][28][29][30][31]. In these types of ZSNs, high voltage gains can be achieved by adjusting the coupled inductors turn ratio. Nevertheless, they are prone to leakage inductances adverse effects, which can cause voltage spikes on switching devices and reduce the efficiency [32].
The enhanced-boost ZSN (EB-ZSN) demonstrated in Figure 1(a) offers a high gain with two switched impedance networks [33]. In comparison with the DA-ZSN and SL-ZSN, the EB-ZSN requires a lower ST duration to obtain the same voltage gain, which results in lower conduction losses and better output waveform quality. However, it suffers from a discontinuous input current and different ground points for the input and the output. These shortcomings have been tackled in the EB-qZSN [34] obtained by properly cascading the qZSN, as shown in Figure 1(b), while maintaining the same boost ability as that of the EB-ZSN with the same number of circuit elements. The active switch used in the EB-ASqZSN [35] is embedded in such a way that the same voltage gain as those of the EB-(q)ZSNs is achievable with two less LC pairs. The voltage gain of the active SL boost-qZSN (ASLB-qZSN) proposed in [36] is similar to those of the EB-(q)ZSNs. The advantages of the EB-qZSN are retained with one less LC pair and one additional active switch. However, the two latter structures are subjected to high voltage stresses on semiconductors. Besides, both require an extra isolated gate driver that can increase the system costs.
In this paper, a new EB-qZSN is proposed in which the realization of the SC concept helps to obtain a high voltage gain. Compared to the competitors, the proposed topology offers a stronger boost ability without any extra active switch. Meanwhile, it retains the advantages of the qZSN such as continuous input current and common ground for the input and the output. Furthermore, it has the advantage of higher power den-  [33]. (b) Enhanced-boost qZSN (EB-qZSN) [34]. EB, Enhancedboost; qZSN, quasi Z-source network sity over the competitors due to its lower size of passive components. Besides, lower rating semiconductors can be applied to this structure. Its low input current ripple allows us to use a low input inductor size. The steady-state performance principles and parameter designs are presented in Section 2 which are followed by the comparative analysis with other high-boost ZSNs discussed in Section 3. Experimental test results on a prototype DC-DC converter are given in Section 4 to verify the theoretical analysis. It should be noted that the proposed ZSN is examined through a DC-DC boost converter just for the sake of simplicity and it can be readily applied to other types of power conversion, the same as traditional ZSNs.

Circuit derivation
Considering the EB-qZSN, illustrated in Figure 1(b), this topology is a cascaded structure of the qZSN [34]. Despite offering a high gain along with the mentioned advantages, the use of four inductors in this structure results in a bulky circuit, which increases the cost and weight of the converter. In order to obtain the same high-boost performance with higher power density, the SC concept is utilized in this topology, as shown in Figure 2, leading to the proposed structure with a stronger boost ability and an improved power density. Regarding the circuit configuration of the proposed topology, it is obvious that this structure is comprised of three inductors (L 1 , L 2 , L 3 ), four capacitors (C 1 , C 2 , C 3 , C 4 ) and four diodes (D1, D 2 , D 3 , D 4 ). It is worth mentioning that the switched-capacitor concept is

Performance analysis
The performance analysis of the proposed topology is carried out by considering two states of operations, ST and Non-ST states, which is a general assumption among all ZSNs. The behaviour of the proposed impedance network will be discussed in both ST and Non-ST states, as shown in Figure 3. In addition, the typical waveforms of elements are presented in Figure 4.
a. ST state: According to Figure 3(a), the ST state occurs when the active switch SW o is turned ON. D 4 is blocking the reverse voltage of C 3 and C 4 . Conduction of SW o lets C 3 to discharge its stored energy to L 3 . D 3 is forward-biased to provide the path for charging C 1 and L 1 . As D 2 conducts, C 1 and L 2 receive energy in parallel from C 2 and C 4 discharging in series. D 1 is blocked due to the reverse voltage Theoretical key waveforms of C 1 and C 2 . C 4 also forms a series-connected path with the input voltage source to charge L 1 . Therefore, during this state, the currents of the inductors and the voltage of C 1 are linearly increased while the voltages of the C 2 to C 4 decrease, as shown in Figure 4. The following voltage equations can be obtained b. Non-ST state: In this operating state, the active switch SW o is turned OFF, as shown in Figure 3(b). D 1 is forward-biased to provide the path for charging C 2 . Therefore, D 2 is reversebiased because it is in reverse parallel connection with C 1 .
As D 4 conducts, the series-connected path composed of the inductors L 1 , L 2 and L 3, and the capacitor C 1 along with the input source discharge the stored energy for supplying the load. Meanwhile, C 3 and C 4 receive energy. D 3 is blocking the reverse voltage of C 3 . Collectively, the voltages of C 2 to C 4 change with a positive slope while the currents of the inductors and the voltage of C 1 decrease to their minimum values. The voltage equations can be written as The average voltage of an inductor over a switching period under steady-state condition is equal to zero. Thus, by applying volt-second balance to the inductors of the proposed topology, the voltage gain (G) can be obtained as where D is the ST duty cycle. As can be seen, the term (2-D) appears as the numerator in the voltage gain equation of the proposed topology. Unlike the SC-qSBN introduced in [25], the realization of the SC concept in the proposed method is such that no additional active switch is needed for the proposed impedance network.

Component parameters design
In order to design the inductors of the proposed topology, the maximum permitted ripple of the inductor currents must be taken into account as a design constraint. By supposing K i % as the peak-to-peak ripple of inductor currents, the required inductances can be calculated based on (4) where V L is the voltage across the inductors during the ST state and T is the switching period. By substituting the corresponding values into (4), the following expressions can be used to design the inductors: The term L B in the above equations is defined by (6), in which P is the nominal power of the converter The required capacitances for the proposed topology can be calculated based on the capacitor's maximum tolerable voltage ripple which is supposed to be K v %. Then, this constraint can be expressed as (7), in which I c is the current flowing through the capacitors during the ST mode Therefore, the required capacitances can be obtained by the following equations: Besides, the size of inductors and capacitors depends on their maximum stored energy [37], which are formulated as Based on (10), the total maximum stored energy of inductors and capacitors can be calculated for the proposed topology as The term W B in (11) is characterized by (12) as Voltage and current stresses of components of the proposed topology are summarized in Table 1, which can be used for semiconductors parameters selection.

CHARACTERISTICS COMPARISON
A comprehensive comparison among the proposed impedance network and the non-transformer-based ZSNs previously introduced such as the DA-qZSN [16], the SL-ZSN [13], the  [33], the EB-qZSN [34], the EB-ASqZSN [35], the HG-SZSN [22], the ASLB-qZSN [36], the HGAS-qZSN [26] and the HVG-qSBN [23] and is carried out, which is represented in Table 2. Obviously, the same input voltage, output power and voltage gain are supposed for all topologies. Among the mentioned ZSNs, the EB-(q)ZSNs, the EB-ASqZSN and the ASLB-qZSN, which have close similarities with the proposed impedance network, are selected in order to conduct a detailed comparative analysis. For the sake of a fair comparison, the boosting ability, components count, passive components size, semiconductors ratings and input current ripple of these ZSNs are investigated.

Boost ability
In Figure 5(a), the voltage gain profile as a function of the ST duty cycle for the proposed topology and the competitors is plotted. It can be observed from this figure that the proposed topology can produce an output voltage, which is almost twice higher than those of the EB-(q)ZSNs and the EB-ASqZSN under the same input voltage and ST duty cycle. Compared to the ASLB-qZSN, the proposed topology takes advantage of the higher boost ability to use lower ST duty cycles. This ability makes the proposed network an appropriate choice for DC-AC applications since it allows us to use higher modulation indices.

Components count
The number of passive/active components of the proposed structure and the competitors are compared, which are listed in Table 2. It should be noted that the components used only in the impedance networks are considered for this study. Compared to the EB-(q)ZSNs, one inductor and one diode are saved by the proposed topology and the same number of capacitors is used. In addition, the proposed topology uses one more capacitor but two fewer diodes and one less power switch in comparison with the ASLB-qZSN. It can be found that the total number of components including active and passive elements used in the EB-(q)ZSNs and the ASLB-qZSN is 13. However, it is 11 for the proposed topology. Considering the EB-ASqZSN, the proposed topology has two additional capacitors and one more inductor. Unlike the EB-ASqZSN, no active switch is used in its structure.

Passive components
In order to conduct a comparative study in terms of the volume of the passive components between the proposed topology and the competitors, the total maximum stored energy of the inductors and capacitors for each impedance network are computed based on (10) and then normalized according to (12). The results are plotted versus the voltage gain, as shown in Figure 5(b) and (c). It is evident from Figure 5(b) that the total maximum energy of inductors of the proposed topology is considerably lower than the competitors. Moreover, Figure 5(c) shows that the total maximum energy of the capacitors in these impedance networks is comparable. The lower overall size of magnetic elements of the proposed topology implies its higher power density compared to competitors.

Voltage and current stresses
In order to better investigate the requirements of semiconductors of the proposed topology, the total switching device power (SDP) is computed. The production of the voltage and current stresses of a switching device is defined as its SDP, which can be regarded as a criterion for measuring the requirements of the semiconductors and consequently, a cost indicator of the system. The corresponding expressions are [38] ⎧ ⎪ ⎪ ⎨ ⎪ ⎪ ⎩ total peak SDP : where i is the number of semiconductors used in the system, I i peak and I i avg are the peak and average currents flowing through the ith semiconductor and V i is its peak voltage stress.
Accordingly, the total peak and average SDP of the proposed topology are calculated and normalized based on the output power. The results are compared with the competitors as shown in Figure 6(a) and (b). It can be seen from Figure 6(a) that the total peak SDP of the proposed topology is lower than that of the ASLB-qZSN for high values of the voltage gain. In addition, the total peak SDP obtained for the EB-(q)ZSNs and the EB-ASqZSN are the same which is lower than those for the proposed topology and the ASLB-qZSN. Figure 6(b) shows that for the whole range of voltage gain, the total average SDP of the proposed topology is the lowest among others.

Input current ripple
To compare the proposed topology with the competitors from the input current ripple profile point of view, Figure 6(c) is plotted assuming the same input inductance for all networks. Obviously, the EB-ZSN is not considered in this analysis due to its input current discontinuity. As can be seen from this figure, the proposed topology offers the minimum input current ripple in comparison with the other three competitors which have a continuous input current. Thus, this feature makes the proposed network a suitable solution for renewable energy applications. Generally concluding, the proposed impedance network with high step-up capability offers improved features compared to its well-known competitors.

PRACTICAL EVALUATION
For verification of the functionality and properties of the proposed impedance network, it is implemented as a simple boost DC-DC converter depicted in Figure 7(a). In this realization,  [7], [31]. The laboratory prototype converter is shown in Figure 7(b). The experimental parameters and test conditions are summarized in Table 3. The ST duty cycle is set to 0.144 which results in a voltage gain of 4 with respect to (3). Therefore, the theoretical output voltage can be calculated as 200 V, when the input voltage is set to 50 V. The measured experimental results are shown in Figure 8. The waveforms, shown in Figure 8(a), are the input and output voltages and currents. As can be seen from this figure, the output voltage is raised to 185 V from the 50 V input voltage which is slightly lower than the expected theoretical value already calculated as 200 V. This little difference comes from the equivalent series resistance of the inductors and the capacitors, the ON-state resistance of the MOSFET and the voltage drop of the diodes, ignored in theoretical boost factor calculation. The continuous input current feature of the proposed topology can be confirmed through the corresponding waveform shown in Figure 8(a). In Figure 8 Table 1 are 92 V, 63 V, 171 V and 29 V, which are slightly higher than those measured from the experimental results due to the parasitic effects of components. The cur-rent waveform of the inductors L 1 , L 2 and L 3 are measured and depicted in Figure 8 Table 1, can be confirmed considering the experimental waveforms shown in Figure 8(d). Another experimental test is carried out for the proposed network with V in = 70 V and D = 0.086. The output voltage and load power are kept constant. The measured results are given in Figure 9. From Figure 9(a), the output voltage can be measured as 189.5 V. It can be found that the difference between the theoretical and measured values of the output voltage is lowered at V in = 70 V when compared to the operation with 50 V input voltage. This is due to the fact that the ST duty cycle requirement and current stresses are lower for the 70 V input voltage operation than those for V in = 50 V, leading to lower conduction losses. Based on Figure 9(b), the voltage across the capacitors C 1 , C 2 , C 3 , and C 4 can be read as 89 V, 77 V, 175 V and 15.3 V, respectively. However, their theoretically calculated values are 95.5 V, 78 V, 182 V and 17.2 V. The experimental waveform of the inductor currents and diode blocking voltages represented in Figure 9(c) and (d) again support the performance principles.
To better demonstrate the difference between the theoretical and experimental voltage gain values of the proposed network, Figure 10(a) is plotted for V in = 50 V and P o = 240 W. As expected, the gap between the calculated and measured values tends to get increased when higher values of voltage gain are required which correspond to higher ST duty cycles and consequently, higher power losses. The efficiency comparison among the proposed network and the competitors is conducted under V in = 50 V and G = 4 for different output power levels and the measured results are illustrated in Figure 10(b). According to this figure, for all ZSNs, the efficiency is decreased when the output power is increased since the conduction losses increase with the rise of output power. In addition, one can observe that the proposed topology offers higher efficiency than those of  the EB-(q)ZSNs and ASLB-qZSN. However, the EB-ASqZSN offers the maximum efficiency compared to the others. In another study, the efficiency of the proposed impedance network as a function of output power is measured for the input voltages of 50 V and 70 V as shown in Figure 10(c). To obtain the output voltage of 200 V, when V in = 70 V, a lower ST duty FIGURE 11 Power loss distribution investigation cycle is needed when compared to that required for the test condition of V in = 50 V which results in lower power losses and improved efficiency. The loss distribution among the components of the under-study ZSNs is obtained using the analytical method in [27], for V in = 50 V, G = 4 and P o = 240 W, and the results are summarized in Figure 11. Evidently, major losses come from the diodes and inductors and the power losses of diodes are dominant for all understudy ZSNs. The lower number of passive components used in the EB-ASqZSN and its lower ST current stress can be mentioned as the main factors in the improved efficiency of this structure which is the highest among others. The higher efficiency of the proposed structure compared to those of the EB-(q)ZSNs and ASLB-qZSN is mainly due to its lower ST requirement along with the smaller size of magnetic elements and the lower number of semiconductors employed in the proposed topology.

CONCLUSION
A new high-boost ZSN is proposed in this paper. The proposed impedance network offers a higher voltage boost factor when compared to the traditional non-transformer-type ZSNs, which implies its lower ST requirement. The lower voltage stress across the semiconductors allows us to use lower rating semiconductors. The lower size of passive components guarantees the higher power density of the proposed impedance network. Thus, improved efficiency is ensured for the proposed method. The continuous input current with a very low ripple and common ground between the input and the output are other advantages of the proposed topology. The operation principle, steady-state analysis, components design guideline and comparison with the conventional high-boost ZSNs were presented. The extensive experiments on a 240-W laboratory prototype confirm the steady-state operational concepts and theoretical results.