A novel gate driver for Si/SiC hybrid switch for multi‐objective optimization

Correspondence Xi Jiang, College of Electrical and Information Engineering, Hunan University, Changsha, 410082, China. Jun Wang, College of Electrical and Information Engineering, Hunan University, Changsha, 410082, China. Email: jiangxi6@hnu.edu.cn; junwang@hnu.edu.cn Abstract A novel gate driver with simple functional and structural integration is proposed here, which splits the input gate signal and outputs two separate signals with a dedicated delay time to drive the two constitutional switches, aiming at the cost-effectiveness and power loss reduction of the Si/SiC hybrid switch. The dependency of the hybrid switch’s thermal and efficiency performance on the parameters of the gate driver are theoretically and experimentally investigated in a 9 kW 20 kHz Si/SiC hybrid switch based boost converter. A novel load current dependent gate control strategy is proposed to be implemented in the proposed gate driver to achieve the high conversion efficiency under light to medium load condition and balanced junction temperature between the two internal devices under heavy load conditions. The experimental results based on a 20 kHz boost converter show that the Si/SiC hybrid switch with the novel gate driver and optimal current dependent control strategy offers a 163% and 10% rise in power handling capability, respectively, compared to that using the all-IGBT device and all-SiC MOSFET device, and yet a considerably lower device cost.


INTRODUCTION
In recent years, the SiC power MOSFETs have become the focus of the medium-voltage device innovation to displace silicon IGBTs because it has lower conduction resistance, faster-switching speed, and higher switching frequency capability [1][2][3][4][5]. Commercially available SiC MOSFET (referred as SiC_MOS) with various voltage ratings (650-1700 V) from several major manufacturers have been continuously penetrating and taking over the realm of Si IGBTs, chasing after the power converter system's compactness and efficiency [6]. Yet despite the promising performance advancement, with a cost-oriented viewpoint, the cost A < sp > -1 < /sp > ($ A < sp > -1 < /)sp > performance poses an obstacle for SiC_MOS primarily due to the costly SiC material and suboptimal fabrication process [7][8]. A cost-effective HyS comprising a primary large current Si IGBT and a small current auxiliary SiC_MOS is proposed, which achieves the cost-performance trade-off in applications [9][10][11][12].
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2020 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology A comprehensive cost analysis was performed in [13] to demonstrate the cost viability of the Si/SiC HyS relative to the SiC_MOS. The current sharing behaviour within the HyS was analysed via simulation in [14,15]. It shows lower switching losses and suppressed oscillations compared to the all-Si IGBT and all-SiC_MOS package layouts, respectively. In [16][17][18][19], the specific gate control patterns are investigated and analysed for the HyS to reduce the switching losses and improve the conversion efficiency of the HyS based converter. In [20,21], a current dependent gate control pattern was reported in voltage source inverter applications to improve the overload capability of the cost-effective HyS.
Although these preliminary studies on the HyS have illustrated their cost superiority, efficiency improvement, and overload capability, some key issues related to the gate control are yet to be solved. First, in some specially designed PWM controller IC applications, the highly integrated design and fixed PWM output channels can't achieve the flexible gate drive patterns of the HyS conveniently. The reported studies on Si/SiC HyS demand two discrete gate drivers to ensure a dedicated gate sequence control with the auxiliary digital control unit, such as FPGA, CPLD, or DSP in the double pulse test circuit or converter applications. However, these solutions compromise the cost-effectiveness of the Si/SiC HyS, and increase the complexity of the HyS based power electronics systems. Therefore, a low-cost gate driver solution is needed for the Si/SiC HyS to achieve the benefit of its cost-effectiveness in practical power conversion applications.
Second, a dominating objective using the above-mentioned gate sequence control is to achieve power loss reduction for the Si/SiC HyS, with insufficient consideration of the safe operation below the thermal limit of its constructive switches. To reduce the switching losses of the HyS, agile sequence control was recommended to achieve the zero voltage switching (ZVS) condition of the main IGBT [13,[16][17][18][19][20][21], where the auxiliary SiC_MOS was turned on prior and turned off shortly after the main IGBT. However, the auxiliary SiC_MOS conducts the fullforward current during these short intervals and undertakes the hard turn-on and turn-off switching operation, which results in the large power loss of the SiC_MOS under the heavy load conditions. The large power loss of the SiC_MOS may result in its junction temperature (referred as T j ) much higher than that of the main IGBT because of its small chip size and large thermal resistance, which put the auxiliary SiC_MOS at risk of over temperature under heavy load conditions. The overheating may induce reliability degradation or thermal breakdown of the SiC_MOS inside the cost-effective Si/SiC HyS if solely relying on this gate control strategy [22][23][24][25][26]. In [27], it adopted the appropriate fixed gate control delay time of the HyS to achieve the sole optimal control objects such as the minimum power loss or balanced T j of the HyS at a specific load condition. However, the gate control objective and corresponding optimal gate delay time need to vary with the load conditions in some load-variable power converter applications, such as PV and wind power. Different objectives of gate delay time control are preferred under different load conditions of load-variable power converters. For example, the power loss minimization of the Si/SiC HyS is preferred under the light or medium load conditions because the T j of its two internal devices are within their safe operating areas. And the thermal performance optimization between its two internal devices is preferred to avoiding the over-temperature risk of its internal devices under heavy load conditions. Therefore, multiple objective optimizations between the efficiency improvement and thermal safety operation of the Si/SiC HyS based power converter operation over a wide output power range needs to be considered in the gate control profile optimization of the Si/SiC HyS.
To solve these problems, a novel gate driver dedicated to the Si/SiC HyS is proposed, which accounts for the costeffectiveness and multiple performance optimization objectives. The load current dependent optimal gate profile control is introduced and implemented using the proposed HyS driver to reduce the power loss of the HyS at light to medium load currents and to keep the two inner devices' T j balance at heavy load current. The operation principle and characteristics of the novel HyS gate driver is introduced and analysed in Section 2. Section  3 introduces the load current dependent optimal control strategy, which is justified using both theoretical and experimental methods employed in this paper. Section 4 concludes the paper.

OPERATION PRINCIPLE AND DESIGN OF THE NOVEL HYS GATE DRIVER
The objective of this section is to propose a novel gate driver structure for the Si/SiC HyS specific control patterns and analyse its operation principle. Figure 1 shows the schematic of the HyS. The HyS's paralleling structure integrates the conduction advantages of the SiC_MOS and the Si IGBT because the SiC_MOS conducts most forward current at small load current condition and the Si IGBT conducts most forward current at large load current condition.
Using the appropriate gate control patterns as shown in Figure 2, the IGBT could achieve the ZVS turning off to reduce the large turn-off switching loss caused by its tail current. Four basic control patterns between the two internal devices of the HyS enable the auxiliary SiC_MOS's ZVS operation or the main IGBT's ZVS operation during the turn-on and turn-off process.
During the switching on transient, the IGBT achieves the ZVS turning on and the SiC_MOS undertakes the hard turning on operation when using the pattern I and pattern II. When using the pattern III and pattern IV, the IGBT undertakes the hard turning on while the SiC_MOS achieves the ZVS turning on operation. The turn-off operation of the HyS is similar to the turn-on operation.  In this work, a novel gate driver solution as shown in Figure 3 is proposed for the HyS to realize the specific gate control patterns (T on_delay and T off_delay ) and achieve its cost-effectiveness and performance improvement. It utilizes a few components to achieve the mutually independent T on_delay and T off_delay for its specific drive patterns.
The proposed gate driver consists of the IGBT drive branch, SiC_MOS drive branch, protection union and two totem-pole drives. The two totem-pole drives are used to directly source and sink the high peak current of the IGBT and SiC_MOS during the switching on and switching off transients. The protection unit is used to block the PWM signals and keep the output be driven low when the short-circuit situation or other faults condition occurs. The SiC_MOS branch and the IGBT branch are used to split the single input signal into two separate output signals with independent adjustable T on_delay and T off_delay , which enable the particular gate drive patterns as shown in

2.1
Turning on process of the gate driver Figure 4 shows the turning on process of the HyS's novel gate driver.
When the output of the U opt (optical coupler) is high level, the capacitor C 1 is charged in the SiC_MOS driver branch. The charging current can be expressed as, where V CC is the positive source voltage, V C1 is the voltage of the capacitor C 1 , R D1 is the equivalent resistance of D 1 . Because R D1 is very small compared with the R 4 and R 2 , R D1 can be ignored in Equation (1). The initial voltage of capacitor C 1 is −V EE . When V C1 is higher than the reference voltage V ref1 , the comparator U 1 outputs high level, which means the SiC_MOS is turned on. The time of the V C1 reaches the reference voltage V ref1 is derived as, In the IGBT branch, similar to the SiC_MOS branch, the current flowing through R 4 and R 3 to charge the capacitor C 2 is given as, The initial voltage of capacitor C 2 is −V EE too. When V C2 is larger than V ref2 , the comparator U 2 outputs a high voltage, which means the IGBT is turned on. The time of the V C2 reaching the reference voltage V ref2 is derived as, T on_delay is the time interval between t on2 and t on1 . It is derived as, when V ref is equal toV ref2 , and C 1 is equal to C 2 , Equation (5) can be simplified as, Equation (6) means that the value of R 3 can determine the length and polarity of the T on_delay between the two internal devices. When R 3 ≥R 2 , the T on_delay is zero or positive, which means the turn-on of the SiC_MOS is equal to or before the IGBT. When R 3 < R 2 , the T on_delay is negative, which means the turn-on of the SiC_MOS is after to the IGBT. The length of the T on_delay is in proportion to the absolute value of the difference between the R 2 and R 3 .

Turning off process of the gate driver
To reduce the IGBT's large turn-off switching loss caused by the tail current, the ZVS turning off of the IGBT is recommended for the Si/SiC HyS. As shown in Figure 2, the pattern I and pattern III are preferred. Therefore, the T off_delay between the two internal devices should be always positive when it is implemented on the novel gate driver. Figure 5 shows the turn-off process of the novel gate driver. When the output of the U opt (optical coupler) is low level, the capacitor C 1 is discharged in the SiC_MOS driver branch. The discharging current can be expressed as, The initial voltage of the capacitor C 1 is V CC . When V C1 is lower than the V ref1 , the comparator U 1 outputs a low voltage, which means the SiC_MOS is turned off. The time of the V C1 reaching the reference voltage V ref1 is derived as, In the IGBT branch, the discharge current of C 2 can be derived as, The initial voltage of the capacitor C 2 is V CC . When V C2 is smaller than the reference voltage V ref2 , the comparator U 2 outputs a low voltage, which means the IGBT is turned off. The time of the V C2 reaching the reference voltage V ref2 is derived as, T on_delay is the time interval between t off1 and t off2 . Because the value of R D2 is very small compared to the R 1 , t off2 is close Dependency of T on_delay on R 3 to zero. Therefore, T off_delay is mainly determined by t off1 .
Equation (11) shows that the length of the T off_delay is in proportion to the value of R 1 .
The resistor R 1 and R 3 are implemented using two adjustable resistors to change the T off_delay and T on_delay , respectively. The other parameters of the gate driver prototype for the HyS are shown in Table 1. Figures 6 and 7 show the measured T on_delay and T off_delay between the two internal devices at various R 3 and R 1 , respectively.
When R 3 < 15 Ω, the polarity of the T on_delay is negative, which means the IGBT is turned on before the SiC_MOS. When R 3 ≥ 15 Ω, the polarity of the T on_delay is zero or positive, which means the SiC_MOS is turned on equal or before the IGBT. The measured results are consistent with Equation (6). When the value of R 1 changes, the polarity of the T off_delay is always positive, and the measured magnitude of the T off_delay is in proportion with the value of R 1 , which is consistent with the Equation (11).

MULTI-OBJECTIVE OPTIMIZATION OF POWER CONVERTER OPERATION
The objective of this section is to propose a multi-objective gate control strategy for the HyS to combine the advantages of the maximum efficiency gate control strategy and thermal balance gate control strategy.
In [27], the gate drive strategy for the HyS can be controlled at the efficiency strategy, and the thermal balanced strategy by adjusting the T on_delay or T off_delay . The efficiency gate control strategy is used to minimize the power loss (referred as P loss ) of the HyS then achieving the high efficiency of the HyS based converter. In the efficiency gate control strategy, the P loss of the HyS could be minimized by setting the appropriate T on_delay or T off_delay at a certain output power rating. Because the T on_delay or T off_delay are determined by the resistor R 1 and R 3 , the efficiency of the Si/SiC HyS based boost converter can be expressed as, = P out P out + P loss_MOS (R 3 , R 1 ) + P loss_IGBT (R 3 , R 1 ) + P loss_others (12) where P loss_MOS and P loss_IGBT are the SiC_MOS's power losses and the IGBT' power losses, respectively. P out is the output power of the HyS based converter. P loss_others is the total power losses of other components, for instance, the HyS gate driver losses, inductor losses, and freewheeling diode losses. Therefore, by setting the appropriate value of the resistor R 1 and R 3 , the high efficiency of the HyS based converter can be achieved.
Because the power loss of the HyS is strongly dependent on the gate control delay times, the balanced junction temperature distribution could be achieved by setting the appropriate gate control delay times of the HyS. Therefore, the thermal balanced gate control strategy is used to achieve the balance T j distribution between the two devices inside the HyS then improving the maximum operation temperature safety margin, and ensuring both devices' T j below the junction temperature limits (referred to as T j_limit )at the heavy P out conditions. The T j of the power device can be estimated using Equation (13).
where R θjc , P loss , T j, and T C are the junction to case thermal resistance, device's total power loss, device's T j, and device's case temperature. Using the thermal balance gate control strategy, the T j of the SiC_MOS and the IGBT are equal distribution. Therefore, the P losses of the SiC_MOS and the IGBT distribution can be expressed as Equation (14) under the thermal balance condition.
ΔT c is the case temperature difference between the two devices. λ R is the junction to case thermal resistance ratio between the two devices. R th(j-c)_MOS and R th(j-c)_IGBT are the SiC_MOS' junction to case thermal resistance and IGBT's junction to case thermal resistance, respectively, which are obtained from their datasheets. Equation (13) shows that the T j of the two devices can be balanced when their P loss has an optimum ratio by setting the appropriate value of the resistors R 1 and R 3 . The optimal P loss ratio of the HyS is also affected by the case temperature deviation and thermal resistance ratio between the two internal devices.

Experiment setup
To compare the efficiency and thermal performance of the HyS at these two different gate control strategies, a Si/SiC HyS based DC/DC boost converter prototype with the proposed gate driver is built and tested as shown in Figure 8 to investigate the efficiency and thermal performance of the HyS under different gate control strategies. The Si/SiC HyS is constituted with the 1200 V/12.5 A SiC_MOS (C2M0160120D) and the 1200 V/40 A Si IGBT (IGW40T120), and the freewheeling diode is the 1200 V/33 A SiC Schottky diode (C4D20120D). The relation between input and output voltage of the boost converter is where V out is the output voltage; V in is the input voltage; D is the duty cycle. In this paper, the input voltage and output voltage are 600 and 300 V, respectively. Therefore, D is 50% constant. The average output current rating of the boost converter can be derived as, Where R load is the load resistor. The maximum output power of the boost converter is designed as 12 kW. Therefore, the minimum R load is 30 Ω and the maximum average output current is 20 A. Table 2 shows the parameters of the HyS based boost converter.
The HIOKI PW3390 is adopted to measure the efficiency of the HyS based boost converter in the steady-state. The FLIR A655sc infrared imager is used to measure the case temperatures of the HyS. Equation (13) is used to calculate junction temperatures of the SiC_MOS and IGBT. The junction to case thermal resistance of SiC_MOS (R th(j-c)_MOS )and IGBT(R th(j-c)_IGBT ) are 0.9 and 0.46 K/W, respectively, which are obtained from their datasheets.

Comparison between the thermal balance control strategy and efficiency control strategy
The two gate control strategies of the HyS has different efficiency and thermal performance under heavy and light load conditions. Under the heavy load condition, when the P out is 9 kW, the measured boost converter's efficiency and estimated T j of the two devices inside the HyS at various values of R 1 and a constant value of R 3 = 16 Ω(means the T on_delay is constant 0 μs) are shown in Figure 9.
When the T off_delay is small, which means the value of R 1 is very small, the converter's efficiency is low. This is because the IGBT's tail current results in large turn-off switching loss. When the T off_delay is large, which means the value of R 1 is very large, the efficiency of the converter reduces especially at the large P out rating. It is because the SiC_MOS's additional conduction loss is increased with the increasing of the gate turnoff delay time especially at the large output current condition. The maximum efficiency of the boost converter is achieved when T off_delay is about 2.2 μs and the corresponding R 1 is around 190 Ω. When the value of T off_delay is very small, the T j_IGBT is much higher than that of the SiC_MOS. This is because of the large turn-off switching loss caused by the tail current of the IGBT at the short T off_delay condition. With the increase of the R 1 , the T j_IGBT is decreased, while those of the SiC_MOS are increased. It is because of the decreasing turn-off loss of the main IGBT and the increasing additional conduction loss of the SiC_MOS with the increasing of the T off_delay . When the value of T off_delay is very large, the T j of the SiC_MOS is much higher than that of the IGBT. This is because the SiC_MOS's large additional conduction loss induces the extremely high T j . A too small or too large value of T off_delay would induce the extremely high T j of the IGBT or the SiC_MOS approaching their T j_limits . When the T off_delay is about 1.6 μs and the corresponding R 1 is about 135 Ω, the balanced T j distribution between the two internal devices can be achieved.
As shown in Figure 9, the maximum efficiency and the thermal balance of the hybrid switch cannot be achieved simultaneously under a certain P out rating. When the HyS is at the maximum efficiency condition, the corresponding R 1 is 190 Ω. However, when the HyS is at the thermal balance condition, the corresponding R 1 is 135 Ω. The maximum T j of the HyS under the balanced strategy is around 49 • C below the T j_limit , while it is only 31 • C below the T j_limit at the maximum efficiency strategy. And these two gate control strategies only induce a conversion efficiency difference of 0.04%. The thermal balance gate control strategy achieves 18 • C lower maximum T j of the switching devices than the efficiency gate control strategy, which is helpful to reduce the over-temperature risk of the HyS. Also, it improves the HyS's maximum output power processing ability and the maximum P out rating of the HyS based converters.
At the light output power rating, when the P out is 3 kW, the measured boost converter's efficiency and estimated T j of the two internal devices of the HyS at various values of R 1 and a constant value of R 3 = 16 Ω(means the T on_delay is constant 0 μs) are shown in Figure 10.
As shown in Figure 10, the converter's efficiency is improved with the increasing of the T off_delay , while the T j of the SiC_MOS and IGBT are not obviously changed with the increasing of the R 1 . This is because the P loss of the HyS is small under the light load condition. The T j of the HyS at two gate control strategies are both very low. Therefore, the maximum efficiency gate control strategy is more applicable to the light load conditions. The calculated maximum T j of the HyS's internal switches and the measured efficiency of the HyS based converter at two gate control strategies under various P out ratings are shown in Figure 11.
When the P out < 6 kW, the efficiency of the HyS based boost converter at the efficiency gate control strategy ≈0.15% higher than that at the thermal balance gate control strategy. It is because the HyS at the efficiency gate control strategy has a smaller total turn-off switching losses compared to the thermal balance gate control strategy.
When the P out is larger than 7 kW, the T j of the HyS at the efficiency control strategy is higher than that at the thermal balance control strategy. This is because the longer T off_delay at the thermal balance strategy results in the larger additional conduction loss of the SiC_MOS then reducing the efficiency. Besides, the larger P loss of the SiC_MOS inducing the higher T j of the SiC_MOS, which restricts the maximum P out handling capacity of the HyS converter. Under the thermal balance gate control strategy, the HyS based boost converter's maximum P out is 10.5% larger than that under the efficiency gate control strategy when the devices' maximum T j reach the T j_limit .

Load current dependent multi-objective control strategy based on the proposed gate driver
If the Si/SiC HyS based converter is solely relying on the efficiency gate control strategy or the thermal balance gate control strategy, there is a severe thermal concern of the HyS's internal switches at the high P out condition or the efficiency reduction of the converter at the low P out condition. To combine the advantages of these two gate control strategies within a wide power range, the load current dependent control strategy based on the gate driver is proposed. Its schematic is shown in Figure 12. In general, the load current, DC-link voltage, cooling strategies, and switching frequency of the converter would affect the power loss of the HyS then affecting the optimal gate control strategies of the HyS. However, in the actual converter applications, the DC-link voltage, cooling strategies, and the switching frequency are relatively fixed. Only the load current is a constantly changing value according to the load conditions.

FIGURE 13
Altering from efficiency strategy to thermal balance strategy Therefore, in this paper, the load current is used as the operation mode selection indicator of the current dependent control strategy to combine the advantages of the thermal balance gate control mode and the efficiency gate control mode within a wide load condition.
To flexibly alter the gate control strategy of the HyS under different load current, R 1 inside the HyS driver is replaced with two switches S 1 and S 2 in series with R 1_T and R 1_η . R 1_η and R 1_T are the optimum R 1 to achieve the efficiency gate control strategy and the thermal balance gate control strategy, respectively. The switches are controlled by a comparator configuration, which compares the output current I load with the threshold current reference I thr . When the output current I load is smaller than I thr , the S 2 is closed and the S 1 is open. The HyS's gate control strategy is changed from the thermal balance strategy to the efficiency strategy, so the converter's efficiency is improved at the light load conditions. When the output current I load > I thr , the S 1 is closed and the S 2 is open. The HyS's gate control strategy is changed from the efficiency strategy to the thermal balance strategy, so the T j of the two devices inside the HyS are kept within their specified temperature range with appropriate thermal safety margin at a high P out level.
As shown in Figure 11, when the P out > 7 kW, the maximum T j of the HyS between the efficiency strategy and thermal balance strategy becomes obvious, while the efficiencies of the converter at these two gate control strategies are almost same. Therefore, the threshold current I thr is selected to be 12 A, which is corresponding to the P out rating of 7.2 kW at the 600 V output voltage condition. The value of R 1_T and R 1_η are selected to be 135 and 190 Ω, respectively.
When the HyS based converter's P out varies from 3 to 9 kW at the 600 V output voltage condition, the measured output voltage V out , the inductor current I L , IGBT's gate voltage control signal V GE_IGBT and SiC_MOS's gate voltage control signal V GS_MOS are shown in Figure 13.
When the average current of the inductor is higher than the threshold current reference of 12 A, the T off_delay between the two internal devices' gate voltage signal is decreased within only one switching period cycle. It means that the discharge resistor is quickly altered from R 1_η to R 1_T , and the HyS's gate control strategy is altered from the efficiency strategy to the thermal balance strategy. And when the converter's P out suddenly varies from 9 to 3 kW, vice-versa.
The measured efficiency of the 40 A single IGBT solution, 40 A single SiC_MOS solution, and the Si/SiC HyS solution with the load current dependent gate control strategy at the 20 kHz switching frequency and various load conditions are shown in Figure 14.
The Si/SiC HyS boost converter's efficiency is almost 0.8% higher than that of the single IGBT based boost converter at the same P out . When the P out is below 6 kW, the efficiency of the single SiC_MOS solution is about 0.29% higher than that of the HyS solution. When the P out is 9 kW, the efficiency of the single SiC_MOS solution is only 0.1% higher than that of the HyS solution. It is explained by that the single SiC_MOS's conduction loss is increased dramatically at the high forward current and high T j conditions because of the positive temperature coefficient of the SiC_MOS, but the conduction loss of the HyS is almost constant because of the main IGBT's drift conduction modulation.
The estimated T j of the 40 A single IGBT solution, 40 A single SiC_MOS solution and the Si/SiC HyS solution with the load current dependent gate control strategy at the 20 kHz switching frequency and various output power ratings are shown in Figure 15.
When the T j reaches the operation T j_limit , the 40A single IGBT based boost converter's maximum P out is only 4 kW. This is because of the large switching loss of the bipolar Si IGBT under high voltage and load forward current conditions. The T j of the single IGBT solution is about 98 • C higher than the HyS solution at 4 kW P out .
When the HyS based boost converter's P out < 6 kW, the single 40 A SiC_MOS's T j is lower than that of the HyS solution. It is because the total power losses of the 40A SiC_MOS are smaller than the Si/SiC HyS solution at the low output current condition. When the boost converter's P out is higher than 6 kW, the single 40 A SiC_MOS's T j is higher than that of the HyS solution. It is because 40 A SiC_MOS's total power losses are increased with the increase of the output current rating. However, because of the drift conduction modulation of the main IGBT, the conduction loss of the Si/SiC HyS is almost constant with the increasing of the output current rating. Besides, when the P out > 7 kW, the HyS's gate control strategy is altered to thermal balance gate control strategy, which enables the optimal ratio of the power loss between two internal devices of the HyS to achieve the lower T j of the switching devices.
When the switching devices' T j reach their T j_limits , the maximum P out of the single 40 A SiC_MOS solution and the HyS using the load current dependent gate control strategy are about 9.5 and 10.5 kW, respectively. The HyS's maximum P out is 10% larger than that of the single 40 A SiC_MOS solutions and is 163% larger than that of the single 40 A IGBT solutions.

CONCLUSION
A novel gate driver solution is proposed for the Si/SiC HyS to achieve its improved cost-effectiveness, high efficiency, and reliable operation in power conversion applications. It makes use of a few components, including resistors, capacitors, and signal diodes to split the single input PWM signal into two separate signals with a specific delay time to realize the HyS's specific gate control patterns. Compared to the conventional two discrete gate drivers realizing with one complicated auxiliary FPGA, CPLD or DSP, its simplified circuitry keeps the costeffectiveness of the Si/SiC HyS and reduces the gate control complexity of the HyS based power electronics systems. The thermal balance gate control strategy and the maximum efficiency gate control strategy of the Si/SiC HyS by setting the specific parameters of the proposed gate driver are extensively investigated and analysed on a boost converter prototype within a wide power range. The HyS's efficiency gate control strategy could minimize its power loss and achieve the high efficiency of the HyS based converter, especially at the low output power rating. However, there is a severe concern of the SiC_MOS's overheating inside the HyS at heavy load condition. The HyS's thermal balance gate control strategy keeps the balanced T j distribution between the two internal devices of HyS within the specified temperature range with appropriate thermal safety margin thus offering a lower operating temperature of the switching devices at the high output power rating. But the maximum conversion efficiency of the HyS can't be achieved at the low output power condition.
To combine the advantages of the thermal balance gate control strategy and the efficiency gate control strategy within a wide load condition, the load current dependent gate control strategy is proposed and implemented in the novel gate driver. The load current is used as the operation strategy selection's indicator of the current dependent control strategy. When the HyS based converter's output power is smaller than a selected reference output power (7.2 kW), the efficiency gate control strategy is selected to achieve high conversion efficiency. When the HyS based converter's output power is larger than the selected reference output power (7.2 kW), the thermal balance gate control strategy is selected to achieve lower operating temperatures of HyS's internal devices and reliable operation of the HyS boost converter. Using the proposed novel gate driver with the current dependent control strategy, the Si/SiC HyS solution exhibits marked improvement in the maximum output power processing ability and thermal properties compared to the single SiC_MOS and single IGBT solutions.