Line current ripple reduction of two paralleled three-phase two-level converter using optimized common-mode voltage injections

This paper proposes a common-mode voltage injection-based pulse width modulation strategy to optimize the AC current ripple of parallel interleaved converters. In general, modulation methods entail a trade-off between switching times and voltage error. Given the redundancy in the available vector sequences, we sequentially minimize the switching times and the voltage error. Speciﬁcally, we propose eight candidate vector sequences with minimized switching times for each 60 ◦ sector. Then, we quantitate the current ripple introduced by the eight vector sequences, and according to the calculations, we split each 60 ◦ sector into eight subsectors, each employs the respectively optimal vector sequence with the minimized current ripple. For implementation, the candidate vector sequences are further uniﬁed by a common-mode voltage injection scheme. The injection depends on the momentary subsector in which the reference lies. Despite the complex geometry of the subsectors, we propose a simple decision procedure that can be easily implemented in mainstream microcontrollers. Compared to the conventional methods, the proposed common-mode voltage injection-based pulse width modulation has a smaller AC current ripple at the same switching loss. The experimental results verify the theoretical analysis and the effectiveness of the proposed common-mode voltage injection-based pulse width modulation


INTRODUCTION
Paralleled interleaved three-phase converter consisting of two two-level voltage-source converters (VSCs) can double the current working rating and the load-carrying capacity [1][2][3]. The two converters are connected to a common DC-link, which reduces the system volume but leads to the zero-sequencecirculating current (ZSCC) [4,5], and common-mode (CM) inductors are inserted before the joint AC connectors (Figure 1) to suppress the circulating current across the converters. Various control methods are proposed to eliminate the lowfrequency ZSCC [6][7][8][9][10].
In past years, many different modulation strategies have been proposed to improve the performance of the parallel converter in various aspects. References [11,12] propose strategies to eliminate line current low-frequency distortion intro-duced by the imbalance in system parameters and the grid voltages. References [13][14][15] develop optimized pulse width modulation (PWM) strategies to suppress the high-frequency ZSCC, which is the main part of ZSCC for the reduction of the size of the CM inductors. References [16][17][18][19][20] focus on the optimization of the AC current ripple using the optimized PWM schemes.
The AC current ripple is the time integral of the real-time error between the output AC voltage and the ideal sinusoidal reference voltage. For grid-connected converters, the AC current ripple and thus the total harmonics distortion (THD) have to meet certain grid codes; for motor drives, the AC current ripple produces high-frequency torque ripple, introducing undesirable acoustic noise and torsional vibrations. Therefore, in these applications, AC current ripple reduction has a high priority, as is reflected by the intensive research in the past years. In the parallel topology, the line current quality depends on the PWM schemes as well as the interleaving angles. References [16,17] demonstrate that the interleaved angle should be adjusted according to the modulation index, in order to minimize the AC current ripple. Considering the complexity of the method, Reference [17] further introduces a quasi-optimal strategy with a fixed interleaving angle of 180 • . The experimental results validate that the shift angle of 180 • yields an AC current ripple close to that of the optimal interleaved angle adjustment.
In addition to optimizing the interleaved angles, many approaches in the literature optimize the PWM schemes for AC current ripple reduction. Reference [18] modulates the parallel converter with the conventional space vector modulation (CSVM) based on two sets of interleaved carriers, which doubles the equivalent output switching frequency and reduces the current ripple. Reference [13] replace the conventional SVM with the active zero-state PWM (AZSPWM), which causes better ZSCC but the same current ripple compared with the CSVM. Reference [14] proposes the modified discontinuous PWM (MDPWM) to suppress the ZSCC, but additional computation efforts are required. Reference [15] develops the interleaved carrier phase-shift PWM (ICPSPWM) for ZSCC suppression, which can be easily introduced into an interleaved parallel converter with an arbitrary number of sub-converter. Although the modulation strategies in [13][14][15] reduce the ZSCC, their current ripples are relatively high.
Reference [19] treats the two paralleled interleaved converter as a three-level converter, and the consequent method (3LSVM) divides the vector plane into 24 subsectors, where three optimized vectors are used, which reduces the ZSCC and current ripple simultaneously. Reference [20] introduces a hybrid PWM (HBPWM) to minimize the current ripple in parallel interleaved converters. This method uses the nearest three vectors to synthesize the reference voltage, which achieves smaller voltage errors than the above modulation strategies. However, the vector sequences in the HBPWM need 33% more switching times per carrier period compared to the other modulation strategies. The consequent limited effective switching frequency deteriorates the output current, limits the system dynamics, and increases the ZSCC peak. Ideally, the reduction of voltage errors should not cost more switching times. The methods in [13][14][15]18,19] maintain fewer switching times but suffer a larger voltage error. The HBPWM causes a smaller voltage error but switches more often. This paper aims to find a better and more general trade-off between the switching times and the voltage tracking error.
The paralleled converter constitutes 19 basic voltage vectors and hence some redundancy among them. We prioritize the switching loss and develop eight vector sequences for each of the 60 • sector. Then, we further quantitate the current ripples of the eight vector sequences. According to the calculations, each 60 • sector can be further divided into eight subsectors, where different vector sequences should be used to reduce the voltage errors. The decision boundary between the candidate vector sequences are complex in shape but allows programming along with a simple flow chart for mainstream microcontrollers. On the other hand, we show that the candidate vector sequences can be unified by the carrier-based implementation, with the only distinction in common-mode voltage injections. Such a finding further simplifies the implementation. We, therefore, name the proposed method the common-mode voltage injection PWM (CMJPWM) strategy. Compared to the modulation strategies except for HBPWM, the CMJPWM has better AC current ripple performance. Compared to the HBPWM, the CMJPWM attains a smaller current ripple except for the region of 0.6 < M < 0.85, where both behaves practically the same; furthermore, the ZSCC of the CMJPWM is much smaller than that of the HBPWM. The experimental results verify the theoretical analysis and the effectiveness of the proposed CMJPWM strategy. Figure 1 demonstrates the topology of the two paralleled converters with the common DC side, and the paralleled AC sides through two CM inductors. The output voltages of the two individual two-level converters are

OPERATION PRINCIPLE OF THE TWO PARALLELED THREE-PHASE INTERLEAVED CONVERTER
where i( = 1,2) means the two individual two-level converters, n denotes the neutral point. s xi (x = a,b,c) is the switch-state function of the xi leg with s xi = 1 when the upper IGBT is on and s xi = 0 when the upper IGBT is off.
An individual three-phase two-level converter has eight available vectors consisting of six active vectors (V 1 -V 6 ) and two zero vectors (V 0 and V 7 ), which are shown in Figure 2(a). When the two converters are paralleled, the equivalent output phase voltages are The available vectors of the paralleled converter can be developed by submitting all the switching states (s xi ) into Equations (1) and (2), which are shown in Figure 2(b). The switch-state combinations of the two individual converters and the resulted 64 available vectors of the paralleled converter are given in Table 1, with VSC1 denoting the first converter ( Figure 1) and VSC2 denoting the second converter ( Figure 1).

OVERVIEW OF EXISTING METHODS
Many modulation strategies have been proposed to improve the line current quality, including CSVM [18], AZSPWM [13], MDPWM [14], ICPSPWM [15], 3LSVM [19] and HBPWM [20]. We briefly review these methods in the first 60 • sector in  The instantaneous voltage error between the actual instantaneous output phase voltage and ideal sinusoidal reference voltage leads to the AC current ripple. The total AC current ripple i rip is a crucial indicator for the evaluation of the threephase output current quality. If the parasitic resistance of the inductor is neglected, the total AC current ripple i rip can be expressed as, where i ripa/b/c and i ripα/β denote the components under threephase and two-phase stationary coordinate systems of the current ripple; u errα and u errβ are the instantaneous voltage error components under the two-phase stationary coordinate system; L is equivalent inductance (L = L s +L cm /2); Δt is the time interval. Equation (3) shows that it is vital to reduce voltage errors (u errα and u errβ ) in order to optimize the current ripple.
In Sectors p1, q1, and r [see Figure 3(a)], the CSVM, AZSPWM, and MDPWM consistently use V l1 , V m1, and V 0 to synthesize the reference voltage, resulting in voltage vector errors V err-l1 , V err-m1 and V err-0 (see Figure 3(b)). For high modulation regions, vector V 0 introduces a larger error; for low modulation regions, V l1 introduces a larger voltage error. Therefore, those PWM strategies always suffer a large voltage error.
In Sectors p1 and q1, 3LSVM uses V s1 , V m1 , and V 0 to synthesize the reference. The corresponding voltage vector errors (V err-s1 , V err-m1 , and V err-0 ) are smaller than those of the above three methods. In Sector r, the 3LSVM uses the nearest three vectors V l1 , V m1 , and V s1 , which possess the smallest voltage errors. With the smaller voltage vector errors in all sectors, the 3LSVM gets a better line current quality than those of the three methods. However, the 3LSVM does not achieve minimal voltage vector errors in Sectors p1 and q1.
The space-vector plane and available vectors of the paralleled converter shown in Figure 2(b) are similar to that of the 3L-NPC converter. Mimicking the nearest three vectors method of a 3L-NPC converter, the HBPWM divides the first 60 • sector into four small regular triangle areas, in which the nearest three vectors are used to synthesize reference. Thus, the voltage errors of the HBPWM are smaller than those of the other methods. However, to select the nearest three vectors, four IGBTs need two more switching times per carrier period. For instance, if the reference is in Sectors p1 and p2 (Figure 3), the HBPWM uses three vectors V s1 , V s2 , and V 0 , and one of the arranged sequences is V s1 (100/111)→V 0 (000/111)→V s2 (000/110) →V s1 (000/100)→V s1 (100/000)→V s2 (110/000)→V 0 (111/000)→V s1 (111/100) in the first half carrier period. As a result, the switches S 11 , S 14 , S 21 , and S 24 in Figure 1 need to switch four times per carrier period. The total switching times of the HBPWM per carrier period is 32, whereas the other methods switch 24×. In addition, due to the twice switching in a carrier period, the HBPWM requires extra hardware to control the gate signals of the IGBTs, which is not required by the other methods.
ICPSPWM adopts phase-shifted carriers among three phases and between two individual converters, which makes the analysis of the voltage vector errors infeasible. The numerical analysis of the ICPSPWM is presented in Section 6.
In summary, the CSVM, AZSPWM, MDPWM, and 3LSVM maintain fewer switching times while having a larger voltage error; the HBPWM has a smaller voltage error at the expense of more switching times.
The switching loss is roughly proportional to the switching times in one carrier period. Therefore, when compared to those of the other methods, the HBPWM needs to reduce its achievable effective switching frequency by ≈25% to keep the same switching loss. The achievable switching frequency is the leading factor of AC current ripple reduction, and the lower effective switching frequency introduces a higher current ripple. Table 1 lists the basic vectors as well as their redundancies; the redundancies further allow targeted performance optimization by the special vector sequences. Intending to reduce the voltage error with minimized switching times, we investigate the available vector sequences in the six subsectors in Figure 3 In addition, vector sequence with the minimized switching times has the following features:

OPTIMAL VECTOR SEQUENCES FOR VOLTAGE ERRORS REDUCTION WITH MINIMAL SWITCHING TIMES
Overlaps of eight vector sequences in the first 60 • sector 1. The switching times per carrier period is minimal. 2. In each switching period, each IGBT is not allowed to switch more than once. 3. At any instance, only one commutation is allowed.
In Sectors p1 and p2 (Figure 3), the vectors V 0 , V s1 , and V s2 are the nearest three vectors, which result in the minimal voltage errors. For minimal switching times, we propose two vector sequences Seq1 and Seq2, as shown in Table 2. The Seq1 and Seq2 achieve the same voltage errors as that of the HBPWM, but with fewer switching times. In Sector r, vectors V l1 , V m1 , and V s1 are the nearest three vectors. Conforming the above rules, we develop Seq7, which also needs fewer switching times than that of the HBPWM. Also, a similar conclusion can be made for Sector s, where Seq8 achieves the same voltage errors but less switching loss than HBPWM.
In Sectors p1, p2, r, and s, the switching times and the vector error can be concurrently optimized. However, in Sectors q1 and q2, the selection of the nearest three vectors (V m1 , V s1 , and V s2 ) contradicts the minimized switching times. Alternatively, we investigate the vectors combinations that introduce the suboptimal errors in Sectors q1 and q2, which are To minimize the switching times, we propose vector sequences (Seq3-Seq6) of these suboptimal vectors, as listed in Table 2. Note that Table 2 only shows the vectors sequence in the first half switching period due to the symmetry.
According to the space-vector synthesis and volt-second balance principle, for three basic vectors used in a vector sequence, only the reference vectors located inside the triangle formed by the terminals of the three vectors can be synthesized, which means that the vector sequences have different linear modulation zones. The available zones of the eight candidate sequences are marked in Figure 4. Triangle ΔOCD pertains to vector sequences Seq1 and Seq2; ΔCDB, ΔDCA, ΔCEB, ΔDEA, ΔCEA, and ΔDEB respectively corresponds to Seq3, Seq4, Seq5, Seq6, Seq7, and Seq8. Figure 4 reveals some overlaps of different modulation zones, which is further detailed in Table 3. We exploit the redundancy in the overlapped regions to optimize the switching sequence.
) Despite the overlap, the optimality of Seq7 in ΔCEA holds because the nearest three vectors construct ΔCEA. A similar conclusion applies to ΔDEB, where the Seq8 uses the nearest three vectors. However, except for ΔDEB and ΔCEA, the optimization of the vector sequence demands further analyses. Sector i (Figure 4) is taken as an example, which is covered by both Seq1 and Seq2. According to the voltage-second balance principle, the duty ratios of the vectors satisfy where u r is the voltage reference vector; Variables d 0 , d s1 , and d s2 are the duty ratios of vectors V 0 , V s1 , and V s2 , respectively; Subscript α/β mean the α-/β-axis components of the corresponding vectors.
The solutions to Equation (4) are  Figure 5 shows the current ripple of different vector timing sequences with a given reference. The mean value of the current ripple over the carrier period is zero. Since vector sequences are symmetric, the AC current ripple also shows symmetry within the first half carrier period. Thus, it is enough to do the analysis in the T s /4 instead of T s /2.
Based on Figure 5, the current ripple i ripα within a quarter of carrier period are where u err1α , u err2α and u err3α are the α-axis components of the voltage vector errors during the intervals.
The current ripple i ripβ within quarter of carrier period are where u err1β , u err2β and u err3β are the β-axis components of the voltage vector errors during the intervals. For the Seq1, the vector errors u err1α , u err2α , and u err3α are: (8) and the vector errors u err1β , u err2β , and u err3β are: For the Seq1, t 1 , and t 2 in Figure 5(a) are: For the Seq2, the vector errors u err1α , u err2α , and u err3α are: and the vector errors u err1β , u err2β , and u err3β are: For the Seq2, t 1 , and t 2 in Figure 5(b) are: To investigate the current ripple performance of Seq1 and Seq2, Equations (6)-(13) are submitted into Equation (3). Two current ripple examples are shown in Figure 6, where we select two reference voltages at M = 0.4 but with different angles (15 • and 45 • ). Figure 6 is the current ripple locus under the α-β coordinate system, where the triangle ΔOP 1 P 2 is the locus of Seq1 in the first T s /4, and ΔOQ 1 Q 2 is the locus of Seq2.
For Seq1, the line segments | OP 1 |, | P 1 P 2 | and | P 2 O | denotes the current deviations caused by the voltage vector errors V err-s1 , V err-s2 , and V err-0 , respectively; For Seq2, the line segments | OQ 1 |, | Q 1 Q 2 | and | Q 2 O | denote the current deviations caused by the voltage vector errors V err-s2 , V err-s1 , and V err-0 . For synthesizing the reference voltage, Seq1 and Seq2 are identical. However, their current ripples vary on the vector angle; particularly, Seq2 results in a smaller current ripple at 15 • ; and the situation reverses at 45 • (see Figure 6).
The root mean square (RMS) value is an important index to evaluate AC current ripple. To generalize the results in Figure 6, we derive the carrier-period-based RMS value of the AC current ripple: Since the ripple curves are symmetric, the calculation of the RMS value can be performed in T s /4, as shown in Equation (14). For a certain u r ( = MV dc /2⋅e jθ ), the carrier-period-based RMS of the AC current ripple is a function of M and θ, where The carrier-period-based AC current ripple RMS of the vector-sequence Seq2 is With Equations (15) and (16), we calculate the current ripple RMS values with two vector sequences and Figure 7(a) shows that neither Seq1 nor Seq2 leads to the less RMS value over the first 60 • . Further analysis reveals an intersection line between the two surfaces in Figure 7(a), i.e.
The solution of Equation (17) is θ = 30 • , regardless of other parameters including T s V dc /L. This leads to a decision boundary that partitions Sector i of Figure 4 into two parts: in Subsector I, Seq2 minimizes the current ripple; in Subsector II, Seq1 minimizes the current ripple (see Figure 7(b)). Note that switching loss has a priority.
With similar approaches, we calculate the current ripple RMS of the Seq3-Seq8 in the first 60 • sector and obtain the optimal vector sequences for the minimized current ripple. The decision boundaries are shown in Figure 7(b), yielding eight subsectors, each pertains to a particular vector sequence.

PROPOSED LINE CURRENT RIPPLE REDUCTION USING OPTIMIZED COMMON-MODE VOLTAGE INJECTIONS
Section 4 develops the vector sequences with minimized switching times for the total current ripple reduction, which occupy different regions in the space-vector plane. It is significant to investigate how to implement the optimal sequences in the mainstream microcontrollers, which uses the carrier-based modulation approach to generate the gate signals. Due to the complementary operation of the lower and upper IGBTs, the development of the carrier-based modulation signal is usually focused on the upper IGBT. Figure 8 shows the carrier-based implementation of the parallel converter using two interleaved carriers, where the d a , d b , and d c denote the conduction duty ratios of S 11 /S 21 , S 13 /S 23 , and S 15 /S 25 , respectively. According to Figure 8(a), if the Seq2 is used (Subsector I in Figure 7), the following expression can be obtained: (18) where d s2 and d 0 are the same as that of (5); u ra , u rb and u rc are the three-phase reference voltages.
According to Figure 8(b), if Seq3 is used (Subsector III), the three-phase carrier-based modulation signals are: (19) When Seq5 is used (Subsector V), the three-phase carrierbased modulation signals are: (20) If the reference is in the Subsector VII, the Seq7 is used, and the three-phase carrier-based modulation signals are:  (18)-(21) reveal that the carrier-based modulation signals in the first 30 • sector consist of two parts: (1) the threephase reference voltages (u ra , u rb , and u rc ), which are identical across the regions, and (2) the common-mode voltage injections, which are different. In Subsector I, the common-mode injection is −u rc ; in Subsectors III, V and VII, the commonmode injection is V dc -u ra .
In the first 30 • sector, u rc is the minimal one of the threephase reference, and u ra is the largest one. Equation (18) can be further unified as where u rmin is the minimal one of three-phase references. Similarly, Equations (19), (20) and (21) are unified as: where u rmax is the maximum one of three-phase references. Similarly, the carrier-based three phase modulation signals in the Subsector II are developed The carrier-based three phase modulation signals in the Subsector IV, VI and VIII are Note that the proposed CM voltage injections in Subsectors I, IV, VI and VIII are equivalent to that of the DPWMMAX method, i.e., injecting V dc -u rmax ; whereas the injections in Subsectors II, III, V and VII amounts to the DPWMMIN strategy, where the injections are consistently set to -u rmin . Equa-tions (22)-(25) further reveal that different subsector should use the optimized common mode injections; the common mode injections in the first 30 • sector are different from that in the second 30 • sector. The common-mode voltage injection of DPWMMAX or DPWMMIN is not optimal for the voltage vector error reduction. However, with the optimized commonmode injections, the proposed method achieves the smallest possible current ripples without increasing the switching loss. In summary, the carrier-based modulation signals are: where u cm is the CM voltage injection; u * rx = u rx /V dc ; u * cm = u cm /V dc . The optimal common-mode voltages depend on the subsectors. It is, therefore, essential to develop a sector identification method. Taking the first 60 • sector as an example, the boundary between Subsectors I and III is If u * ra − − u * rc > 1/2, we inject V dc -u ra ; else inject -u rc . Similarly, the boundary of Subsectors II and IV is If u * ra − − u * rc > 1/2, we inject -u rc ; else inject V dc -u ra . Note that the boundary of 0-30 • sector and 30-60 • sector is u * rb = 0. If u * rb < 0, reference is in the 0-30 • sector; else the reference is in 30-60 • sector.
In addition, we investigate the boundary conditions of the subsectors in the remaining vector plane (60-360 • ) and develop a simple flow chart to select the optimal common-mode injections, which is shown in Figure 9, where u rmid is the middle one of three-phase references.

PERFORMANCE COMPARISONS BETWEEN CONVENTIONAL STRATEGIES AND PROPOSED CMJPWM STRATEGY
We compare CMJPWM to the conventional methods to complete the review in Section 3.
As discussed in Section 3, when evaluating the current ripples, it is essential to adjust the switching frequency to ensure the identical switching loss. Therefore, the resultant frequencies of conventional methods should be normalized to the switching frequency of the CMJPWM (f = 1/T s ): the resultant switching frequency of HBPWM should be f/2; the CSVM, AZSPWM, MDPWM, and ICPSPWM have a resultant switching frequency of 2f/3. The resultant switching frequency of the 3LPWM depends on the modulation index. If the modulation index <2/3, the frequency is set to that of the CSVM. If the modulation index is > 2/3, the equivalent frequency is set by ) .
(29) Equation (29) tells that in the high modulation region where the track of the reference in the first 60 • is exclusively located in the Subsectors VII and VIII, the 3LSVM is equivalent to the proposed CMJWPM strategy.
With the normalized frequency, we investigate the AC current ripples under the conventional methods and calculate the carrier-period-based RMS values defined by Equation (14) using a similar approach introduced in Section 4. Figure 10 shows the results under different modulation indexes (M = 0.3, 0.6, and 0.9), which demonstrate that the proposed CMJPWM is superior to the methods except for HBPWM in terms of the carrierperiod-based RMS defined by Equation (14). In addition, Figure 10 reveals the CMJPWM has a better performance than that of HBPWM when M = 0.3; there are some intersections between the HBPWM and the CMJPWM in high modulation region. The indicator defined by Equation (14) has its limit when evaluating the performance of the HBPWM and the CMJPWM. It is essential to investigate the current ripple in the whole fundamental period, evaluating the current quality of a modulation strategy. Thus, the fundamental-period-based RMS of the current ripple is a key parameter, which is defined as Equation (30) and is a function of M only: We calculate the RMS values defined by Equation (30) of the proposed method and the conventional methods and obtain that of the ICPSPWM through a simulation in Matlab. It can be seen from Figure 11 that the proposed CMJPWM has much lower RMS values than the methods except HBPWM in the whole modulation region; the proposed CMJPWM has a lower RMS value than the HBPWM except the region where M ranges from 0.6 to 0.85; when M ranges from 0.6 to 0.85, the RMS values of the CMJPWM is close to that of the HBPWM. Therefore, in most of the modulation region, the proposed CMJPWM has a lower AC current ripple than the HBPWM.
In addition, the ZSCC is another critical indicator of the paralleled converter, which determines the size of the CM inductor. We also compare the ZSCC of the proposed CMJPWM to that of the conventional methods. Figure 12 demonstrates that the CSVM and HBPWM have the largest ZSCC peak, which is 2.25× larger than that of the proposed CMJPWM; the other four methods have the minimal ZSCC peak, which is threefourth of that of the proposed CMJPWM.

EXPERIMENT VALIDATION
The proposed CMJPWM strategy is implemented on an experimental prototype (see Figure 13), which is constructed by a TMS320F2808 DSP, IGBTs (SKM200GB12T4, SEMIKRON), IGBT gate drivers (SKYPER 32 PRO R, SEMIKRON), and DC-link capacitors (SHP-1100-400-FS, EACO). To focus on the modulation strategy validation, we configure the prototype shown in Figure 13 as a parallel interleaved inverter with a common DC-link and a three-phase resistive AC load. The DClink voltage is built through a three-phase diode rectifier. Two common-mode inductors are used to be the three-phase filters and suppress the ZSCC. The main parameters of the prototype are shown in Table 4. The conventional PWM strategies CVSVM, AZSPWM, 3LSVM, MDPWM, ICPSPWM, HBPWM, and the proposed CMJPWM techniques are tested on the experimental prototype. In order to get the performance of the proposed CMJPWM in a wide modulation index range, we select two typical modulation   To further validate the theoretical analysis in Section 6, more tests are conducted with modulation indices, and the results are shown in Figures 28 and 29. Figure 28 shows that among the conventional methods, HBPWM has a smaller line current ripple than CSVM, AZSPWM, ICPSPWM, 3LSVM, and MDPWM, and Figure 29 shows that AZSPWM, ICPSPWM, 3LSVM, and MDPWM have a smaller ZSCC peak than that of HBPWM. According Figures 28 and 29, the proposed CMJPWM achieves as good line current ripple as HBPWM, both of which are smaller than CSVM, AZSPWM, ICPSPWM, 3LSVM, and MDPWM. Besides, the proposed CMJPWM significantly reduces the overly large ZSCC peak of the HBPWM. When compared to the AZSPWM, ICPSPWM, 3LSVM, and MDPWM, the proposed CMJPWM has a much smaller line current ripple, and its ZSCC peak is close to those of AZSPWM,

CONCLUSION
This paper proposes a common-mode voltage injection-based pulse width modulation (CMJPWM) method to optimize the AC current ripple of the paralleled interleaved converter. We investigate the available vector sequences of the paralleled converter and propose eight candidate vector sequences with minimized switching times. To implement the optimal vector sequences, we split the first 60 • sector into eight subsectors, each of which should use the optimal vector sequence with the minimized current ripple. The carrier-based modulation signals reveal that the optimal common-mode injection into the

FIGURE 28
The fundamental-period-based ripple RMS values

FIGURE 29
The ZSCC peak values of different PWM methods major region. If the modulation ranges from 0.6 to 0.85, the current ripple of the HBPWM is close to that of the CMJPWM. Meanwhile, the ZSCC of the CMJPWM is much smaller than that of the HBPWM over the entire modulation region. Therefore, the overall performance of the CMJPWM is better than that of the HBPWM. The experimental results verify the theoretical analysis and the effectiveness of the proposed CMJPWM strategy.