Estimation of the capacitor voltages in flying capacitor multi‐level converters

Funding information Universidad Autónoma de Nuevo León, Grant/Award Number: PAICYT IT-1069-19 Abstract Flying capacitor multi-level converters use charged capacitors as a critical element. For proper operation, the capacitor voltages must be known and regulated. Direct measurement is straightforward, but when the number of required measurements is high, this is a complicated approach. This paper introduces an estimation method for n capacitor voltages. The scheme is based on a system of (n + 1) equations, which is defined in a way that it incorporates information of the actual capacitor voltages and open-loop estimates of the capacitor voltages. The solution of the system gives the best estimates of the capacitor voltages in the sense of least square errors. The method requires only output voltage and output current sensors and its computational burden is low, saving cost and design efforts, and simplifying the hardware system. The performance of the proposed scheme is evaluated experimentally in a 9-level flying capacitor chopper, where the estimates are used by the voltage balancing strategy and by the output current controller.


INTRODUCTION
Multi-level converters were introduced with the invention of the neutral-point-clamped (NPC) converter [1]. Later, other multi-level topologies, as the flying capacitor multi-level converter (FCMC) [2], the cascaded H-bridge multi-level converter (CHBMC) [3], and the modular multi-level converter (MMC) [4], were developed. In one hand, multi-level converters allow using power electronics semiconductors in voltage levels higher than the blocking voltage of the individual power semiconductors, enabling the use of power electronics in middle and high voltage applications. Moreover, its output voltage is composed of more than two discrete voltage levels, improving its quality. On the other hand, each specific multi-level topology has a particular structure, but share a basic operating principle. In this sense, multi-level converters use a set of voltage sources which are series-connected by power semiconductors to get the multi-level output voltage waveform. There are several ways in which the voltage sources and power semi-conductors can be arranged, given raise to the known multi-level topologies [1][2][3][4]. In general, charged capacitors define the voltage sources in multi-level converters, which needs a control loop to ensure the required voltage level at each capacitor. Furthermore, each This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology topology has specific requirements concerning the capacitor voltages which are needed to get a proper and safe converter operation. When the number of capacitors is high, maintaining the required voltage level at each capacitor is a challenging task. Due to its high-quality waveforms and its capability to operate at higher voltages than individual semi-conductors, multilevel converters are attractive for applications in medium or high-voltage levels [5][6][7][8]. More recently, the FCMC is proposed for applications where high-density power and highquality waveforms are required. In [9], an active power filter based on a 3-level 4-leg FCMC is proposed, and in [10] a flyingcapacitor (FC) bridge is incorporated into a full-scale converter for direct-drive wind turbines. Also, in [11] an FC-MMC is presented for medium-voltage motor drives, and in [12] an FC fly back converter for pulsed power applications is proposed. Furthermore, 7-level FCMC are applied to single-phase inverters in [13] and as a power factor correction front end boost converter in [14]. Also, in [15] a single-phase N-level FC multilevel rectifier is used in a solid-state transformer, and a compact dual-output inverter is presented in [16]. Finally, in [17] a 9-level FCMC for electric aircraft applications is proposed and a 13-level inverter is presented in [18]. These applications demonstrate the potential of the FCMC using a high number of levels, where the property of natural balance is used to achieve the required voltage at each capacitor. Several works have studied this property, and proposed techniques to improve its dynamics, especially at start-up when the input dc voltage increases from zero to nominal value [19][20][21][22]. Furthermore, closed-loop strategies are used to improve the capacitor voltage balancing dynamics [23][24][25][26][27][28]. Indeed, the closed-loop control of the capacitor voltages is an area actively researched. Most of the proposed techniques require to know the capacitor voltages to implement a closed-loop control strategy. Direct measurement is straightforward, but when the number of capacitors is high, direct measurement becomes a complicated task. In this case, it is more convenient to use a reduced number of sensors, and indirectly measure the voltages using estimation or observation techniques. In this sense, there are several proposals to simplify the capacitor voltage measurement task [29]- [41]. Estimation and observation techniques are based on measurements of the output current or the output voltage or both, which combined with the system model allow to know the capacitor voltages using a reduced number of sensors. Some proposed techniques are based on non-linear theory [29][30][31] or sliding mode approaches [32,33]. These approaches have fast response, and good performance under parameter uncertainty, but its complexity restraint their real-time implementation, and tuning the observer gains is difficult, especially when they are implemented in discrete time with relatively big sample times. In [33], a discrete sliding mode observer is proposed, and some guidelines are given to select the gains. Other proposals use the output voltage measurement to measure the capacitor voltages indirectly. Indeed, there exist some switching states where only one capacitor determines the output voltage; in this case, the voltage of that capacitor is equal to the measured output voltage. In [34], this is applied to an MMC, using a single voltage sensor for a subset of modules. Whenever only one of these modules is active, then its voltage is equal to the measured output voltage. If more than one module is active, then the voltages are estimated using an open-loop approach. The error introduced by the open-loop estimation is corrected by enforcing a measure sequence at predefined times, which introduces additional complexity to the scheme. A similar approach is used in [35] with a flying capacitor converter. Here, the estimation scheme is presented using the formalism of Petri nets. Furthermore, [36] propose to divide the modules in an MMC into several groups and use one voltage sensor for each group. Several cases are considered to estimate the voltage of each group accurately. In these schemes, correction of the open-loop induced errors needs the introduction of a particular measuring sequence, which adds complexity to the system.
Other estimation schemes are based on linear quadratic schemes [37][38][39][40]. Since the output voltage is a linear combination of the capacitor voltages, then several consecutive measurements are expressed as a system of linear equations -the solution of this system gives an estimate of the capacitor voltages. In [37], the capacitor voltages in an FCMC are estimated using this principle. An over-determined system of equations is defined from consecutive output voltage measurements, and then solved to find an estimate of the capacitor voltages, however, a unique solution is not always possible. Moreover, this approach needs a high sampling rate, putting restrictions for its real-time implementation. In [38], an adaptive linear neuron and a recursive least-squares algorithm are proposed. Both algorithms are similar in the sense that both need a design parameter for the correction term, but the recursive least-squares needs a higher number of calculations. Another linear quadratic estimation scheme is proposed in [39] to estimate the state variables in an MMC. Also, in [40], the Kalman filter is used in an MMC, where a linear combination of the capacitor voltages models the output voltage, and the Kalman filter is used to estimate the capacitor voltages from the output voltage measurements. Also, an open-loop predictor combined with a simplified version of the Kalman filter is proposed in [41]. Here, the open-loop prediction of the output voltage is compared with its measurement to introduce a correction term in the open-open loop estimation. The scheme is applied to an MMC and verified by numerical simulations.
In this paper, we propose a simple and efficient estimation scheme for the n voltages of the FCMC. The scheme is based on a system of (n + 1) equations requiring only output voltage and current sensors, saving cost and design efforts, and simplifying the hardware system. The first equation models the output voltage as a linear combination of the capacitor and input voltages, the other n equations contain the information of previous estimates. The solution of the system, in the sense of least-square-errors, gives the best estimate of the capacitor voltages, at each sampling time. Among its distinctive features, we have its straightforward implementation, its low computational burden, good precision, and the absence of adjustment parameters. Moreover, the scheme can be applied to converters with an arbitrary number of voltage levels. Furthermore, the scheme is validated by simulation and experimentally in a 9-level flying capacitor chopper, where the estimated voltages are used to implement a closed-loop control strategy for the capacitor voltages and output current.
The rest of the paper is organised as follows. In Section 2, the general model of a multi-level converter is developed. After developing the model, the estimation scheme is introduced in Section 3, and its application to a 9-level flying capacitor chopper is presented in Section 4. Then in Section 5, the test bench is described and simulation results are presented in Section 6. The experimental results are analysed in Section 7, and the conclusions outlined in Section 8.

MULTI-LEVEL CONVERTERS
Multi-level converters can be represented by the serial connection of controlled voltage sources, as shown in Figure 1, where in most cases, charged capacitors are used instead of voltage sources. The control input of the j th voltage source is a discrete function, j ∈ {−1, 0, 1}. In this section, we develop a general model for a multi-level converter; the model is intended to develop the estimation scheme for the capacitor voltages.

2.1
Multi-level converter model Figure 1 shows an equivalent circuit of a multi-level converter, modelled as the serial connection of controlled voltage sources. From Figure 1, the output voltage is defined by a linear combination of the n voltage sources, expressed as where j (t ) and v c j (t ) are the commutation function and the voltage of the jth voltage source, respectively. The commutation function j (t ) is defined by the control signals of the power semiconductors. When capacitors are used to define the voltage sources, their voltage dynamics is given by where v c j (0) , i c j (t ) and C j are the initial voltage, the current and the capacitance of the j th capacitor, respectively. In this model we assume that the equivalent series resistance (ESR) of the capacitors is negligible. The current through the j th capacitor is defined by the output current and the commutation function as where i o (t ) is the converter output current.

Discrete model
Let us suppose that the converter variables are known only at discrete instant times t = kΔt , where k ∈ ℕ and Δt is the time elapsed in between sampling instants. Then, at time k, the output voltage is given by where (⋅) k are variables defined at instant time k. Furthermore, the capacitor voltages are given by where we assume that Δt is small, such that i k c j ≈ i k−1 c j . Then, introducing Equation (3) into Equation (5), the capacitor voltages are expressed as Equations (4) and (6) are the basis for the estimation scheme that is introduced in Section 3.

ESTIMATION OF THE CAPACITOR VOLTAGES
Let us assume that at time k the output current and output voltage are measured, the commutation functions are known, and an estimate of the capacitor voltages at time k-1 is available. Then, from Equation (6), the a priori (or open-loop) estimation of the capacitor voltages, at time k, is given bŷ where (⋅) k_ is the a priori or open-loop estimate at time k for the variable (⋅). On the one hand, Equation (7) gives estimate of the capacitor voltages that are subject to the well-known limitations of openloop estimators; on the other hand, the measurement of v k o is a linear combination of the actual capacitor voltages at time k.
Then, the open-loop estimates and the output voltage measurement can be used to form the following system of equations: The over-determined system (8) can be solved to find the best estimates of the capacitor voltages in the sense of least-squares errors (LSE) at time k. The (pseudo-) solution to system (8) is given byV where k T is the transpose matrix of the design matrix k , ( k T k ) −1 is the inverse matrix of ( k T k ) which is a square (n × n) matrix called the pseudo-inverse of k ; the (pseudo-) solution of (9) is unique if rank( k ) = n which is always assured by the last n rows of k . Indeed,V k c represents the best estimation of the capacitor voltages at time k, in the sense of LSE. These estimates are obtained by combining a measurement of the output voltage (a linear combination of the actual capacitor voltages), and the open-loop estimates of the capacitor voltages. Note that the introduction of the output voltage measurement allows adding a closed-loop correction term to the openloop estimates.

Estimation algorithm
Given the sparsity of matrix k , system (9) can be solved to find an explicit equation for each estimate. Solving Equation (9), each estimate is given bŷ wherev k c j is the estimate of the j th capacitor voltage, with j = 1, … , n; v k_ c j is the a priori (or open-loop) estimate of the j th capacitor voltage, as defined by Equation (7); v k o is the measured output voltage, andv k_ o is the a priori estimation of the output voltage, given byv Thus, the proposed estimation scheme is defined by Equations (7), (10), (11) and (12), where Equation (10) is the explicit equation for each estimate, Equation (7) represents the a priori estimates of the capacitor voltages, Equation (11) gives the a priori estimate of the output voltage and Equation (12) represents the gain for the correction term. Indeed , the output voltage measurement allows to add a correction term based on the actual capacitor voltages which improves the open-loop estimates.

ESTIMATION OF THE CAPACITOR VOLTAGES IN A FLYING CAPACITOR MULTI-LEVEL CONVERTER
In this section, we apply the estimation algorithm to FCMC, which equivalent circuit is shown in Figure 2. It consists of n voltage sources, that can be connected in series by the action of the switches control signals, d j andd j . Proper operation of the converter requires complementary control signals, d j andd j [2].
Let define the control signal applied to the upper switch of cell j as d j ∈ {0, 1}, where 0 and 1 define the off and on state, respectively. Then at time k, the following commutation function is defined where k j ∈ {−1, 0, 1}. Furthermore, the output voltage is defined as a linear combination of n voltage sources, as where v k c j , from j = 1, … , n − 1, and v k c n are the flying capacitor voltages and the input voltage at time k, respectively.
Moreover, the capacitor voltages are given by Equation (15), for j = 1, … , n − 1, represents the flying capacitor voltages, and for j = n it represents the input voltage source; if the input voltage is considered constant between sampling times, then the second term in the right hand side of Equation (15) is equal to zero for j = n. Moreover, the following voltage values at each capacitor are needed: where v * c j , n and V DC are the voltage reference for the j th capacitor, the number of commutation cells and the input voltage, respectively. These capacitor voltages are necessary to distribute the input voltage between the series-connected switches evenly, and also to obtain an output voltage composed of discrete voltage levels of equal magnitude. Indeed, these capacitor voltages are a necessary condition for the proper and safe converter operation [2]. Equations (14) and (15) are identical to Equations (4) and (6) of the generic converter described in Section 2, and therefore, the estimation of the capacitor voltages can be achieved applying the method presented in Section 3. Thus, the estimation of the capacitor voltages is given by Equations (7), (10), (11) and (12), where the commutation functions are defined by Equation(13).

TEST BENCH
In this section, we explain how the proposed estimation algorithm is used in a 9-level FCMC system. Figure 3 shows a 9level FCMC, which is composed of eight commutation cells. Each commutation cell is defined by a pair of complementary switches (SjU and SjL) and capacitor C j , where j = 1, … , 8; note that for j=8 that capacitor defines the input voltage V DC . The cell switches are controlled by complementary control signals dj, dj ′ , where j = 1, … , 8. The complete system includes the control strategy for the capacitor voltages balance and the output current controller, as shown in Figure 4. The test bench is composed of a 9-level FCMC configured as a chopper with and R-L load. The estimation and control algorithms are periodically executed on a dSPACE 1104 control board, with a sampling period T s = 75μs. First, the estimation algorithm estimates the capacitor voltages using the methodology explained in Sections 3.1 and 4. Next, the output current controller calculates the output voltage level to regulate the output current. The current controller is based on a finite control set model predictive controller (FCS-MPC) [35]. To find the voltage level needed for the output current regulation, we calculate, one step ahead, the output current, considering each available voltage level, as follows: where v x j are the available voltages, defined as v x j = jV DC n for j = 0, 1, … , n andV DC is the estimated input voltage; T s is the sampling period and = L∕R is the load constant time. Then, a cost function, , is defined as the absolute value of the predicted output current error for each available voltage level where i * (k+1) o is the reference current. The voltage level that minimises Equation (19), is selected as the required voltage level v * x . Finally, the balancing strategy selects the switching state that balances the capacitor voltages and ensures the required voltage level, simultaneously. This strategy uses the capacitor and input voltages estimates to decide if the capacitor voltages must be increased or decreased, according to Equation (16). The capacitor voltage balancing strategy is based on the redundancy of switching states and directly provides the control signals for the FCMC [28]. Note that the switching frequency is variable, but the estimation process is executed periodically at a sampling frequency of f s = 1∕T s . This simplifies the estimation process because for calculating the a priori capacitor voltages, using Equation (7), Δt is always equal to T s . When modulation schemes are used, the switching frequency is constant; however, the duty cycle and the duration of the switching states are variable, which imposes some restrictions on the estimation scheme. In this case, it is necessary to use a sampling frequency much higher than the commutation frequency to prevent the loss of data when the duration of the switching states is small. However, for some duty cycles, there will be some switching states that can not be detected in detriment of the accuracy. Also, higher the sampling frequency, more computational power will be necessary to shorten the algorithm execution time.
It is worth to mention that with the used balancing strategy [28], the maximum voltage ripple in the capacitors is given by

SIMULATION RESULTS
In this section, we present simulation results to evaluate the performance of the proposed estimation algorithm. The nominal parameters of the test bench system are given in Table 1.The software Matlab/Simulink is used to simulate the system, where the power converter simulation uses a time-step of 1μs and the estimation algorithm, output current controller and capacitor balancing strategy are executed sequentially each 75μs. The ref-erence current, i * o , is defined as a sinusoidal waveform with a dc offset where = 2 f with f = 60Hz. First, we show results using direct measurements of the capacitor and input voltages, assuming measurements without noise. Figure 5 shows the input voltage and capacitor voltages measurements. The capacitor voltages evolution is in a quasi-balanced manner as required for proper and safe converter operation. Figure 6 shows the output voltage and current and their respective total harmonic distortion (THD); also the current tracking error is shown, where we can observe that in steady-state it is about ±0.1 A.
Next, we present results using the estimates instead of direct measurement of the voltages. Figure 7 shows the measured and estimated capacitor voltages and the estimation error. The capacitor voltages evolution is similar to the obtained with direct measurements (see Figure 5). The estimation error is less than 1V, even if at start-up, it reaches higher values than in steady-state. However, the capacitor voltages evolution is quasi-balanced, ensuring the overstress on switches is limited to safe values. Figure 8 shows the output voltage and current and its respective THD, which values are practically the same as those obtained with direct measurements. Regarding the current tracking error, shown in Figure 8(c), it remains the same as the obtained with direct measurements. However, in practice, the measured signals are corrupted by noise. To study the effect of noise in the system, we have added white noise to the output voltage and current measurements; the output voltage measurement noise has a maximum value of ±2V, while for the output current we considered a maximum noise value of ±100 mA. Figures 9 and 10 show the effect of noisy measurements. We observe a quasi-balanced capacitor voltages evolution at start-up, and an estimation error in steady-state of about ±1.5 V -Note that the estimation errors are calculated using the measurement of the capacitor voltages without noise. Regarding the THD of the output voltage and current, it is 16.52% and 2.46%, respectively, and the output current tracking error is about ±0.15A. Table 2 summarises the obtained results, where we have added an ideal case (first row), where constant voltage sources replace the capacitors; the voltage sources values are given by Equation (16). Also, results with an equivalent series resistance (ESR) of 10 times the nominal value are shown in the last row.

EXPERIMENTAL RESULTS AND DISCUSSION
In this section, we present the results obtained in a 9-level flying capacitor chopper. Figure 4 shows the block diagram of the experimental test system and Fig. 11 shows the 9-level FCMC laboratory prototype. The experimental system consists of a 9-level flying capacitor converter, a variable dc voltage source, voltage and current transducers, a function generator and a dSPACE 1104 control board. The nominal parameters of the experimental system are given in Table 1. For the experimental test, we use an amplitude modulated dc biased sinusoidal at 60 Hz. The reason behind this choice is to test the estimation algorithm with a variable output current, which at some intervals will need only a reduced number of voltage levels. The dc voltage source is connected to the converter input; the function generator provides the output current reference; the control board (dSPACE 1104) receives measurements of the output voltage and current, and executes the estimation and control algorithms each 75 μs. First, the capacitor voltages are estimated, then, the output current regulation loop calculates the required voltage level and finally, the capacitor voltages balance algorithm takes place, generating the control signals for the converter switches.

Steady-state performance
In this test, we evaluate the performance of the estimation scheme in steady-state. For that purpose, we compare the measured capacitor voltages with the estimated voltages. Note that the measured values are corrupted by noise, with maximum values of about ±2.0 V. Furthermore, we investigate the performance of the capacitors balance algorithm, which uses the estimates of the capacitor voltages. The capacitor voltage references are given by (16), where in the test bench V DC is replaced by its estimate, If the capacitor voltages are in accordance with Equation (21), the off-state switch voltages are given by  Figure 12 shows the converter output variables (top) and its zoomed view (bottom). The upper trace shows the output voltage, which is composed of equal magnitude discrete voltage levels. In one hand, this is possible only if the capacitor  voltages are correctly balanced, as defined in Equation (21). On the other hand, the balance of the capacitor voltages is possible only if the capacitor voltages are accurately estimated. Additionally, the middle trace shows the output current, and the bottom trace shows the output current error. Note that the output current is an amplitude modulated waveform. This is intended to test the estimation scheme with output voltages that contain all or only some of voltage levels. The output current error is bounded around ±0.2 A, as observed in the bottom trace of Figure 12, indicating that the current control loop is also operating correctly. This initial test shows the excellent performance of the estimation scheme and demonstrates its potentiality in a real application. Following, we show further results to evaluate the performance of the estimation scheme in steady-state. Figure 13 shows the estimated capacitor voltages and the estimation errors. As shown, the estimated and measured voltages are very close. Note that the measured and estimated values used to compute the errors have noise introduced by the measurement process, causing to observe a high-frequency component in the errors. Also, note that the input voltage has a low-frequency ripply, which is due to the output current variation. But its estimate is in concordance with the measured value. Furthermore, Table 3 shows the average voltage and maximum voltage ripple, ΔV c Max , of the estimated and measured voltages; the theoretical maximum voltage ripple is given by Equation (20). As shown, the estimated and measured values are similar; the average values of the estimated and measured voltages are both in close concordance with the value defined in Equation (21), which confirms the good performance of the estimation scheme. Regarding the maximum observed voltage ripple, if we consider the noise introduced by the measuring process, it is also according to the theoretical value.

Performance at start-up
In this test, we evaluate the performance of the estimation during the start-up process. During the start-up process, the input voltage, V DC , changes from zero to its steady-state value. The main objective is to keep the off-state switch voltages at safe values, eliminating possible overstress on the semi-conductor switches. In this sense, the implemented closed-loop balancing strategy uses the estimated voltages to generate the control signals that ensure the balance of the capacitor voltages. Therefore, the estimation scheme must provide accurate estimates to keep the balance of the capacitor voltages, ensuring the safe operation of the converter switches during the start-up process. Figure 14 shows the response of the system during the startup process. The top window shows the estimated and measured capacitor voltages -when the input voltage starts to rise, the estimation errors are higher, but the capacitor voltages reach their desired equalised values in a quasi-balanced manner, at t ≈ 0.2s-(see the middle window in Figure 14). The estimation error is higher when some of the capacitor voltages have the same value. Indeed, the converter model is valid only when v c1 < v c2 , … , < v cn . If this is not the case, the estimation scheme is not able to accurately estimate the capacitor voltages.
The bottom window of Figure 14 shows the off-state switch voltages. The voltage of the switches reaches its required value, as defined by Equation (22), at about 0.2 s. Note that in this test, no particular procedure has been considered in the closedloop balancing strategy to start-up the converter. The same

Performance under an input voltage change
In this test, we evaluate the performance of the estimation scheme when the input voltage changes its value (it is increased or decreased) from a given steady-state value. In such events, the balance strategy, that uses the estimates of the capacitor voltages, must properly operate to prevent overstress of the converter switches. Especially during the voltage rise, the correct capacitor voltages balance ensures the off-state switch voltages at secure values. Also, if an external control loop uses the estimated voltages, then an accurate estimation is desired to minimise the effect of these transients on the external control loop. Figure 15 shows the response of the system when the input voltage decreases from 100 V to 70 V, and then it returns to its  steady-state value of 100 V. At Figure 15(a), the input voltage, the estimation errors and the off-state switch voltages are shown at the top, middle and bottom traces, respectively. The estimation errors during the transients are similar to the steady-state errors, meaning that the estimation scheme can accurately estimate the voltages of the capacitors under this type of transients.
We notice a small increase in the off-state voltage of the switches, which means that the capacitor voltages are slightly unbalanced. This unbalance happens because the output current during the transient has a small value. A small output current limits the voltage dynamics, preventing to accurately follow the input voltage dynamics according to Equation (21). Nevertheless, the accuracy of the capacitor voltages estimation is practically the same as in steady-state. Notice that unlike what happened in the start-up transient, in this case, the estimates of the capacitor voltages are accurate. This accuracy is possible because the voltages of the capacitors are such that v c1 < v c2 , … , < v cn , ensuring the validity of the used model. Furthermore, Figure 15(b) shows the output current, which remains regulated as long as there is enough voltage for its control; otherwise, the control strategy will use the maximum available voltage to ensure the minimum possible error in the output current. These results confirm the excellent performance of the estimation scheme when a transient occurs in the input voltage.

Performance with uncertain parameters
In this test, we evaluate the performance of the estimation scheme when the capacitance values are uncertain. Indeed, the actual capacitors in the laboratory prototype have nominal tolerance of ±10%. In a first test, a capacitance of 300 μF is assumed, while the nominal value is 390 μF . Figure 16, shows the estimated capacitor voltages and the estimation errors, and Table 4 shows the average voltage and the maximum voltage ripple of each capacitor voltage. Both measured and estimated values are similar, which means that estimated values are as good as the measurements even if the assumed capacitance values are only 77% of the nominal values. The estimation errors are small, ensuring an accurate balance of the capacitor voltages, as shown in the top window of Figure 16. Moreover, data in Table 4 shows that the average capacitor voltages (measured values) are accurately regulated according to Equation (21).
In a second test, the capacitance values are 15% higher than the nominal values (i.e., C = 1.15C nom = 450μF ). Figure 17 shows the estimated capacitor voltages and the estimation errors, and Table 5 shows the average voltages and the maximum voltage ripple of the estimated and measured voltages. The mean values of the capacitor voltages are according to

Assessment of the computational burden
The computational burden account for the number of arithmetic or logic operations needed to implement the estimation algorithm. In this sense, the proposed algorithm requires about 48 sum operations and 42 multiplications to estimate eight voltages. We could say that for n estimates the number of additions and multiplications is given approximately by (6 × n) operations, which is a low computational burden. Moreover, in terms of execution time the computational burden is determined by the processor speed.

CONCLUSION
In this paper, an estimation scheme for the capacitor voltages in FCMC is introduced and experimentally tested in a 9-level laboratory prototype. The scheme is based on a system of n + 1 linear equations where the unknowns are the capacitor voltages. The first equation models the output voltage measurement as a linear combination of the actual capacitor voltages; the following n equations hold the information of the open-loop estimates. This approach allows estimating the capacitor voltages and input voltage at each sampling time. Indeed, the approximate solution of the system gives the best estimates of the voltages in the sense of least-squares-errors. Also, the solution is unique because the design matrix always has full column rank. Additionally, because the design matrix is sparse, it is possible to have explicit equations for each estimate. The resulting equations are simple, without any adjustable parameter. The only system parameter needed for the estimation is the capacitance value, but its impact in the estimate precision is low. Furthermore, the estimation scheme was incorporated into a closed-loop control to regulate the output current and the capacitor voltages-the estimates of the capacitor voltages are used by the current regulation controller and by the capacitor voltages balance strategy. The obtained results confirm the excellent performance of the estimation scheme under different operating conditions (i.e. transient state, steady-state, and uncertain capacitance values). The obtained results show that the estimates can be used instead of direct measurements, saving the cost and design efforts, simplifying the hardware system, which is very attractive when the number of levels is high.
Finally, its simplicity and low computational burden make feasible its use in multilevel converters with a large number of capacitors. It allows using only one voltage sensor instead of n physical sensors, which is especially attractive when the number of required levels is high.