Model predictive control of a hybrid stacked multicell converter with voltage balancing and fault tolerance capability

Funding information Post China Postdoctoral Science Foundation, Grant/Award Number: 2020M673282; Fundamental Research Funds for the Central Universities, Grant/Award Number: 2682020CX51; State Key Laboratory of Traction Power, Grant/Award Number: 2020TPL-T13; Department of Science and Technology of Sichuan Province, Grant/Award Number: 2020ZYD010 Abstract Due to the merits of low conduction losses and superior output power quality, a hybrid stacked multicell converter (HSMC) was put forward as a competitive alternative in the medium/low-voltage high-efficiency applications. A nine-level HSMC (9L-HSMC) can be seen as a combination of a five-level SMC (5L-SMC) and two-level half-bridge, and proper modulation and control strategy are essential for the HSMC to obtain the optimal output performance. This work develops a finite control-set model predictive control (MPC) strategy for 9L-HSMC to balance the capacitor voltages and maintain the desired outputs, rendering the absence of the linear regulator and pulse width modulation (PWM) modulator possible. The fault-tolerant operation can also be achieved flexibly when open-circuit faults occur at active bidirectional switches in the 5L-SMC bridge, and the performance is verified by simulations. Finally, experiments under several typical operating conditions are implemented to verify the effectiveness of 9L-HSMC with the developed MPC strategy.


INTRODUCTION
In recent years, multilevel converters draw more and more attentions in the high-voltage large-power industry areas because of their paramount features, such as reduced device stress, superior power quality and lower power losses [1,2]. Three typical multilevel topologies such as neutral-pointclamped (NPC), flying-clamped capacitor (FCC) and cascaded H-bridge (CHB) converters have been widely employed in various energy conversion systems. The NPC and FCC topologies suffer the inherent drawbacks of numerous devices requirement and voltage unbalance of capacitors, which limit their higherlevel (over five) applications [2].
Hybrid multilevel converters (HMCs) have been put forward by combining the merits of traditional converters, which are suitable for medium-and low-voltage applications due to their high efficiency [3][4][5]. Several HMC topologies, such as active NPC ANPC), nested NPC and stacked multicell converter (SMC), have been proposed for various applications [6][7][8]. The SMC is proposed by stacking flying capacitor (FC) cells, and it draws great attentions from the academic and industrial communities because of its dramatic characteristics, such as An SMC is composed of FC-based cells, and a three-level Ttype converter can be recognised as the SMC with two FCbased cells which own the advantage of low conduction losses [9,10]. In low-voltage applications and switching frequency below 35 kHz, the three-level T-type converter is better than NPC [10].
Several FC-based HMCs have been put forward for mediumand low-voltage applications with reduced devices, compared with traditional SMC [11][12][13]. The required number of dc sources is halved by connecting two additional switches in parallel with the original SMC [11]. To reduce the number of highfrequency switches, a mixed structure of SMC was presented by increasing four switches that work at fundamental frequency [12]. Moreover, a hybrid SMC (HSMC) was put forward to reduce the high-frequency switches in [13], which is devised by introducing merely two low-frequency switches. As a result, the number of high-frequency switches in such HSMC is cut by half while the amplitude of output voltage is doubled. The nine-level HSMC (9L-HSMC) can be divided into a five-level SMC (5L-SMC) bridge and a two-level half-bridge (2L-HB; see Figure 1), where the switches of 5L-SMC and 2L-HB bridges work at high frequency and fundamental frequency, respectively. Therefore, low power losses and good output quality are obtained for 9L-HSMC. Some other HMC topologies with reduced power devices have been proposed for high-voltage applications, such as grid-connected system [14], high-frequency link converters [15] and high-voltage direct current transmission [16]. This work is devoted to explore the overwhelming merits of the HSMCs, in terms of capabilities of voltage balancing and fault tolerance.
Capacitor voltage balancing is a critical issue for 9L-HSMC, and each FC voltage must be controlled at their references. Typically, the FC voltage can be balanced by utilising multicarrier-based pulse width modulation (PWM) along with redundant state selections [17][18][19]. However, these PWMbased approaches are incapable of realising multiple control targets simultaneously, such as switching frequency optimisation and fault-tolerant operation. Model predictive control (MPC) has the merits of intuition, simplicity and flexibility, offering adaptability, robustness and fast dynamic response [20]. The linear regulators and modulators are absent, thereby reducing control complexity significantly. Additionally, the multipleobjective optimisation can be realised by selecting proper weighting factors in a single cost function. In recent years, the MPC technique has been adopted and designed to meet specific requirements in various power converters [21][22][23] and motor drives [24,25]. To obtain a good quality of outputs, some improved MPC approaches were put forward for various HMC topologies. A selective harmonic elimination MPC method was presented in [26] for the multilevel converters. In [27], a simplified two-stage MPC was put forward for an HMC that is a combination of ANPC with a floating Hbridge. In [28], a virtual space vector MPC was proposed for a three-phase seven-level HMC. A new Lyapunov-based MPC was developed for a seven-level packed U-cell grid-connected inverter [29].
To the best of the author's knowledge, no study on the MPC of HSMC has been reported in prior literature. For this motivation, this work develops an MPC-based control strategy for 9L-HSMC to obtain the desired outputs as well as balancing the capacitor voltages. First, the proposed MPC method is implemented by constructing a discrete-time model of 9L-HSMC, where a cost function is defined to achieve the control objectives by evaluating all the available switching states. Afterwards, the optimum switching state that minimises the cost function will be applied for 9L-HSMC at the next sampling interval. Furthermore, with the help of bidirectional switches, the fault-tolerant operation can be achieved by using the proposed MPC-based control strategy, thereby enhancing system reliability. The postfault configurations, operation principle and control strategies are put forward. The blocking voltages and power losses, including switching loss and conduction loss, are studied for the 9L-HSMC. Finally, the feasibility of the proposed control strategy for 9L-HSMC is validated by experiments under several typical operating conditions.

Operation modes
The main circuit of 9L-HSMC is drawn in Figure 1, where v a denotes the output phase voltage between terminals X 1 and X 2 , and i a is positive phase current (i a > 0). In this circuit, T 11 , T 12 , T 21 , T 22 and their complementary switches of 5Lbridge work at high-frequency PWM mode, and T 1 , T' 1 of 2Lbridge work at low-frequency mode. If the dc-bus voltage is equal to V dc , the reference values of the dc-link capacitor voltages and FC voltages must be controlled at V dc /2 and V dc /4, respectively. The 9L-HSMC has 18 redundant states V 1 ∼V 18 as listed in Table 1, where the characters S 1 , S ij (i = 1, 2; j = 1, 2) are switching functions of power switches T 1 and T ij , respectively. The capacitor currents and their effect on the capacitor voltages are illustrated for the states V 1 ∼V 18 . Due to the state redundancy, the voltage balancing of FCs can be realised by selecting an optimum state to charge/discharge the FCs. During the positive half-cycle of current, states V 7 and V 8 can be selected to output V dc /4, whereas the effect on the C f2 under states V 7 and V 8 will be opposite. Likewise, we can select V 11 and V 12 to output -V dc /4, and this will result in discharging and charging the C f1 , respectively. The output voltage v a can be synthesised to acquire the nine levels (±V dc , ±3V dc /4, ±V dc /2, ±V dc /4, 0) by selecting the proper switching state among the redundant states.
To emphasise the operating principle, Figure 2 indicates the current paths when 9L-HSMC operates at the positive half-cycle of current for outputting voltage levels ±V dc and ±V dc /4. One can find from Figures 2(a) and (b) that states V 1 and V 18 have no impact on the FCs. As can be observed from Figures 2(c) and (d), states V 7 and V 8 are selected to output V dc /4, which results in charging and discharging C f2 , but no current flows through C f1 . Likewise, states V 11 and V 12 discharge and charge C f1 , but no current flows through C f2 as depicted in Figures 2(e) and (f).
Note: "↑" and "↓" denote the charging and discharging of capacitors, respectively; "n" represents no current flows through the capacitors.

Potential characteristics
Any level general topology of the HSMC can be realised by stacking more FC-based cells in the SMC as demonstrated in Figure 3. Although the switches in higher-level HSMC can stand medium voltage, it is also suitable for low-voltage applications to obtain high-quality outputs because of its low power losses. If the dc-bus voltage is rated at V dc , the voltages of C fn1 and C fn2 must be controlled to track the reference V dc /(2 × n) as expressed by The number of output voltage level for the n-cell HSMC is 4n + 1. For example, when the stacked FC-based cell n = 3, the reference of C f11 and C f12 is V dc /3, while the reference of C f21 and C f22 is V dc /6, and the output voltage level is (±V dc , ±5V dc /6, ±2V dc /3, ±V dc /2, ±V dc /3, ±V dc /6, 0).
The application of the HSMC for three-phase areas (motor driver, flexible alternating current transmission systems (FACTs) etc.) can be realised like the traditional CHB. The dc-bus voltage can be supplied by one single dc source or three isolated multi-secondary transformers [14], and the recommended circuit of three-phase 9L-HSMC is presented in Figure 4. If it is applied to a compensating device, such as STATCOM, dynamic voltage regulator (DVR) and active power filter (APF), the dc source can be replaced with capacitors.
One of the critical issues of the HSMC is maintaining the FC voltage at the reference value during all conditions since it determines the quality of output voltage and current. Fortunately, there is a large number of redundant states that can be selected flexibly to balance FC voltages while obtaining the desired outputs. On the other hand, the number of power switches will be increased with the increase of voltage levels as can be seen in Figures 1 and 3. The failure rate of power switches will be increased in the long run, which may reduce system reliability. Therefore, proper modulation and control methods are required to obtain good performance while enhancing the system reliability.
For these above motivations, an MPC-based control strategy is developed for the 9L-HSMC to realise FC voltage balancing control and post-fault operations in the case of switch faults.

PROPOSED CONTROL STRATEGY
Due to its simplicity and flexibility, the MPC is a good option to reach the multiple control objectives in the HSMC system. Therefore, an MPC-based strategy is developed for the HSMC to minimise the errors between the outputs and their references. To achieve better tracking performance, the normalisation of state variables is implemented, which is used as an additional optimisation criterion in defining the cost function and tuning parameters.

Mathematical foundations
According to the switching states listed in Table 1, the output voltage v a and current i a can be formulated with v f1 , v f2 and switching functions S 1 , S 11 , S 12 , S 21 and S 22 : where R and L represent the load resistance and inductance, respectively. The currents that flow through the FCs and dc-link capacitors can be expressed by where i f1 (t), i f2 (t), i c1 (t) and i c2 (t) are instant currents of the FCs and dc-link capacitors; i a (t) is the instant load current. The capacitor voltages can be therefore obtained as The continuous-time model described in Equations (4) and (5) is the first step to implement the estimations and predictions of the state variables for the proposed MPC algorithm. According to the mathematical foundations given in Equations (2) to (5), the control variables (phase current and capacitor voltages) are interrelated with each other. Therefore, the discrete-time predictive models of state variables can be derived from the mathematical formulations illustrated below.

Prediction of state variables
The control vector of state variables is defined as , and the continuous-time model described in Equations (2) to (5) must be transformed into discretetime expressions to generate the predictive models of the state variables. The backward Euler algorithm is adopted to approximate the first-order derivation of the current i a , and it has where T s is the sampling time of the MPC, and i a (k), i a (k+1) are the measured currents at the kth and (k+1)th sampling interval, respectively. Substituting Equations (3) into (6) gives the predictive model of the phase current as The predictive model of the output voltage v a (k+1) is obtained by discretising the continuous-time model in Equation The discrete-time model of capacitor currents at k instant can be estimated by the following expressions: By reusing the discretisation in the prediction step, we have the predictive model of capacitor voltages v fx (k+1) and v cx (k+1) (x = 1, 2) at k+1 instant as

Normalisation of state variables
As for the standard MPC algorithms, the optimum state that minimises the discrepancy between the references and measurements will be selected after the prediction of state variables.
To improve the tracking performance, the dissimilarity of the variation ranges (high volts of voltage and low amperes of current) should be considered [21]. In this study, the normalisation is implemented by defining the maximum variations ΔV max and ΔI max of the capacitor voltages and load current, respectively. Substituting Equations (9) into (10) and arranging it, yield where ΔV f1 (k) and ΔV f2 (k) are the variations of the FC voltages between two adjacent sampling instants. According to the states  Table 1, the maximum variations can be obtained as Similarly, the maximum variations of the dc-link capacitor voltages can be expressed as Substituting Equations (8) into (7) and making an approximate, the maximum variation of current i a can be calculated by The variations of different state variables are depicted in Figure 5, where the variations are located within the maximum values ΔV cmax , ΔV fmax and ΔI max for any measured point.

Optimisation criterion
The proposed MPC-based controller works in discrete time at each sampling time, which is too large than the fundamental cycle. Therefore, the reference current at (k + 1)th sampling interval is generally approximated to be the value at kth. In actual operations, the reference current i a * can be determined to realise the specific targets in different applications such as the renewable energy conversion systems, where the reference current is generated by the outer-loop controller for the real and reactive power regulation. Afterwards, the fourth-order Lagrange extrapolation method is adopted to extrapolate the reference phase current at k + 1, yielding where variables with superscript * denotes reference value. The defined cost functions contain the control objectives of minimising the deviation between the phase current i a (k+1), the capacitor voltages v cx (k+1), v fx (k+1) (x = 1, 2) and their where v c * and v f * are reference signals of the dc-link capacitor voltages and FC voltages, and they are, respectively, V dc /2 and V dc /4. λ is the weighting factor that should be properly tuned to meet the performance requirement. The total harmonic distortion (THD) of the phase current and the maximum deviation of the FC voltages are measured by varying the value of λ from 0 and 1. The current THD is the lowest when λ = 0.3, and the FC voltage deviation decreases considerably as the value of λ increases. In this case, the current THD is 1.52% while the FC voltage deviation has a relatively low value of 0.2 V. Therefore, λ = 0.3 is selected in all the following simulations and the experimental measurements. The flowchart of the proposed MPC for the 9L-HSMC system is shown in Figure 6, where the reference current i a * can be generated by the outer-loop controller for achieving the specific targets, such as real power regulation, harmonic elimination and torque control [20]. To avoid the influence of the outer control loops, a pure sinusoidal wave with a peak value of I a * is selected to generate the reference current for the HSMCs in the studies, and then the equivalent modulation index m can be calculated by m = I a * √ R 2 + ( L) 2 ∕V dc . Therefore, the reference output current can be formulated as The implementation of the MPC approach can be divided into the following steps.

Measurements: The phase current i a (k) and capacitor volt-
ages v c1 (k), v c2 (k), v f1 (k), v f2 (k) are measured at k instant. 2. Estimations: The switching states designated to 9L-HSMC at (k-1)th interval are not changed over one sampling cycle, which is used in the estimation of output voltage v a .

Predictions:
The obtained predictive models of phase current and capacitor voltages in Equations (7) to (10) utilise the estimations to predict the state variables at the (k+1)th sampling interval. 4. Optimisation algorithm: The predictions of the phase current and capacitor voltages are evaluated for each redundant state that is listed in Table 1. Then, the optimum state which minimises the defined cost function g should be applied to the HSMCs at the beginning of next sampling instant (i.e. k+1), and the control performance will be observed at (k+2)th sampling instant.

Fault-tolerant operation
Due to their initial characteristics, the multilevel converters have a redundant switching state, which can be used flexibly to realise fault-tolerant operation by reconstructing the topologies and switching state combinations [30,31].   12 , respectively. The reference voltage of C f1 and C f2 is V dc /4, and the 5L-bridge can still be able to output five levels ±V dc , ±3V dc /4, ±V dc /2, ±V dc /4 and 0 as presented in Table 2.
As shown in Figure 7(c), when the OCF occurs at the outer switch T 12 or T' 11 , the 5L-bridge is degraded to a four-level bridge (viz. T-type nest NPC [31]). Here the switches T 11 , T 21 and T' 22 operate complementary with T' 12 , T' 21 and T 22 . In this case, the reference voltage of C f1 and C f2 should be set as V dc /3, and seven voltage levels ±V dc , ±2V dc /3, ±V dc /3, 0 can be obtained from Table 3.
As shown in Figure 7(d), the 5L-bridge changes into a threelevel FCC bridge when OCF occurs at both inner and outer switches. In the post-fault circuit, (T 11 , T' 12 ) and (T 21 , T' 22 ) are two complementary switch pairs. The reference voltage of C f1 and C f2 is controlled at V dc /4, and then five levels ±V dc , ±V dc /2, 0 will be generated from Table 4.
As can be seen from Figure 7, the number of available switching states will be reduced in the post-fault circuits, which may decrease the balance capability of the FC voltages. Since the fault-tolerant operation is an emergency case, the proposed MPC strategy is modified for the HSMCs to achieve continuity operation. The system reliability is enhanced with reduced capacitor voltage balancing ability and deterioration of power quality. Figure 8 shows the fault-tolerant operation modes for the HSMC under OCFs at bidirectional switches. Note that, since the switches of 2L-HB bridge work at the fundamental frequency, the probability of fault is assumed quite lower than that   of high frequency (HF) switches in 5L-SMC bridge; thus, the circuit faults at the low frequency (LF) switches were not considered. Due to the limitation of space, the diagnosis methods of OCFs are not discussed and they can be found elsewhere [30]. After circuit faults of inner/outer bidirectional switches are localised, the corresponding fault-tolerant control must be activated. It should be noted that the proposed control strategy will not be applicable when OCF occurs at the switches T 11 , T 21 , T' 21 and T' 12 . In this case, the zero level cannot be output in the 5L-bridge while maintaining the balance of capacitor voltages.

Fault-tolerant operation
In order to obtain the performance of the MPC-based faulttolerant control strategy, simulations were conducted. The dc bus is supplied by a constant dc power source V dc = 50 V, and the ac output terminal is connected in series with a linear RLload (R = 15 Ω, L = 4.3 mH). The dc-link capacitor C d and the FC capacitor C f are 2200 and 1000 μF, respectively. The sampling frequency of the controller is set as 20 kHz. Figures 9  and 10 plot the voltage, current and FC voltages of 9L-HSMC with OCF occurring at the bidirectional switches. It can be seen that the current i a has no significant deterioration under faulttolerant operation, and it shows good tracking performance even during the transient cases.
As shown in Figure 9(a), when the OCF occurs at the inner switches, 9L voltage v a remains attainable and the FC voltages v f1 , v f2 are balanced with a voltage ripple of ∼0.4 V. Due to the reduction of available switching states, there exist unexpected commutations in the phase voltage v a in order to balance the FC voltages. Figure 9(b) displays the waveforms when the OCF occurs at the outer switches, the v f1 , v f2 , are regulated from V dc /4 to V dc /3 after 50 ms, and then v a changes from 9L to seven level.
Once the OCF occurs at both inner and outer switches, the 5L-SMC bridge will be degraded to the FCC bridge. As shown in Figures 10(a) and (b), if the v f1 , v f2 are controlled at V dc /6 and V dc /4, the v a changes from 9L to seven level and 5L, respectively. Although the voltage level of v a decreases, the amplitude of i a is not decreased and the FC voltages are still balanced and maintained at their reference values. The capacitor voltages v dc1 and v dc2 are balanced by using the proposed control strategy under the normal and inner switch fault modes, and the simulation waveforms are presented in Figure 11, whereas they do  not need to be balanced under the faults of outer switches T' 12 and T 11 since there is no current flow through the neutral point. Moreover, the THD of the output voltage v a and load current i a is studied under different operation modes by using the fast fourier transform (FFT) toolbox, and the results are listed in Table 5. The THD values are higher than that of the normal mode, which is acceptable since the fault modes are emergency cases. Overall, the desired outputs and fault-tolerant operation are both achieved as expected by using the proposed MPCbased strategies.

Blocking voltages of switches
The voltage stress is an essential part of the design of inverters, as it determines the volume and costs. The blocking voltage of the power device is defined as the maximum voltage stress across the device during the OFF state. The blocking voltages for each switching state under the normal and faulttolerant modes are presented in Figure 12. The LF-cell switches have to stand full dc-bus voltage V dc , while the blocking voltage of HF-cell switches varies from 0 to 2/3V dc . It is possible to equip the HSMC topologies with different types of switches to explore their advantages (e.g. Si insulated gate bipolar transistors (Si-IGBTs) for HF cell and SiC metalor (SiC-oxideor (SiC-semiconductor field-effect transistor (SiC-MOSFET) for LF cell).

Dynamic performance
In order to verify the dynamic performance of the 9L-HSMC with the proposed control strategy, transient simulations were conducted with a step change of reference current. The results are shown in Figure 13, where the output voltage and current

Power losses distributions
To evaluate the effectiveness of the proposed control strategy, the power losses of the 9L-HSMC including switching loss and conduction loss are studied. The conduction losses are determined by the on-state equivalent resistance and forward voltage drops, while the switching losses are estimated by the linear approximation of voltage and current through kth switch [32]. The power losses were calculated by MATLAB/Simulink based on the constructed loss models. The main circuit of the 9L-HSMC is constructed by using Infineon switches (FZ400R17KE3) with a rating of 1700 V/400 A. To make the loss analysis reasonable, the dc-link voltage is set as V dc = 1 kV in this section. Figure 14 portrays the percentage of power losses distribution for 9L-HSMC. As can be observed from  Figure 14(a), the conduction losses percentage of LF switches in 2L-HB is higher than that of HF switches in 5L-SMC. However, the percentage of switching losses in LF switches is merely 0.2% as clearly shown in Figure 14(b). Figure 15(a) shows the bar chart of power losses of IGBTs and body diodes. As can be seen from Figure 15(a), the T' 11 and T 22 have the largest losses that amount to 100 W, as they work at high frequency during a whole cycle for balancing the FC voltages. It is worth noting that the switching losses of the LF switches are negligible, and they have the least total losses. Finally, the efficiency curve versus a wide range of equivalent modulation index m (from 0.1 to 0.9) is plotted in Figure 15(b), where the efficiency is depicted with different values of modulation index.

EXPERIMENTAL VALIDATIONS
In order to verify the developed MPC for the HSMCs, an experimental platform was built as photographed in Figure 16. The experimental HSMC system is composed of the main circuit, sensor circuits, driving boards and controller. The Infineon IGBTs (IHW15N120E) and electrolytic capacitors are used to construct the main circuit. The dc voltage is supplied by a constant dc source, while the ac output is a series connected with a pure resistor load through a filtering inductor. A real-time board/module MicroLabBox is used to implement the analog digital conversion (ADC), logical calculations and control approaches. The detailed parameters used in the experiment are summarised in Table 6.

Steady-state performance
Initially, the HSMC works under steady-state condition, and the experiment results are plotted in Figures 17 and 18. Here, the modulation index m is 0.85 and an RL-load (R = 15 Ω, L = 4.3 mH) is connected between the output terminals. Figure 17(a) shows the output voltage v ao between ac terminal X 1 and the neutral point O, whereas the phase voltage v a and current i a are given in Figure 17(b). As can be seen from Figure 17, the output voltage v ao and v a are obtained well with five and nine levels, respectively. Figure 18 shows the deviations of capacitor voltages (Δv dc = v c1 -v c2 ; Δv fc = v f1 -v f2 ), phase current and its reference signal. It can be found that the value of Δv dc , Δv fc are nearly null and the current tracking

Dynamic performance
In order to unveil the dynamic performance of the MPC for the 9L-HSMC, several typical transient cases are investigated. Figure 19 presents the experiment waveforms of capacitor voltages under the start-up and step-changing of the dc-bus voltage V dc from 50 to 35 V. As can be seen from Figure 19, the v c1 , v c2 and v f1 , v f2 are fully balanced well and maintained at their reference values V dc /2 and V dc /4, respectively. Figure 20(a) and (b) demonstrate the experiment results with step decreases of the equivalent modulation index m (from 0.85 to 0.6) and (from 0.85 to 0.4), respectively. As can be seen from this figure, the voltage level is degraded to seven and five, respectively. But, the FC voltages are balanced well, and no significant voltage ripples are observed even during the transient process. In addition, the measured results with the output frequency f out changing from 50 to 100 Hz are presented in Figure 21, which tells us that the tracking performance of the output voltage v a and current i a are verified, and no voltage spikes occur in the FC voltages, even during the transient process.

Sensitivity of parameter mismatches
The effect of parameter mismatches on the response of the MPC-based HSMC is also investigated, and the R and L that

FIGURE 21
Experiment results of 9L-HSMC with step changing at output frequency f out from 50 to 100 Hz are required for the estimations and predictions are evaluated. Figure 22(a) shows the converter response to a step increase of R from 7.5 to 20 Ω (nominal value is 15 Ω). In this case, the MPC operates with underestimated and overestimated resistance for the estimation and prediction calculations. The modulation index is adjusted to ensure the phase current to be controlled, thereby avoiding the influence on the balancing of FC voltages. Furthermore, we experimentally checked the performance of HSMC when the inductance is mismatched from 2.15 to 9 mH (nominal value is 4.3 mH), and the related curves are demonstrated in Figure 22(b). In this case, some undesirable switching transitions have occurred at some voltage levels. Using the MPC strategy, the sinusoidal phase current and balanced FC voltages remain achievable, though some high-frequency spikes exist in the output voltage.

CONCLUSION
This paper proposes an MPC strategy for the HSMCs with low conduction losses and superior output quality. The MPC strategy is designed to balance the capacitor voltages while obtaining the desired outputs. These control objectives are achieved by minimising the single costs function, making the complex linear regulators and PWM modulators absent. Moreover, the flexibility of the fault-tolerant operation can be reached by using the MPC-based control strategy, which enhances the system reliability. Power losses of 9L-HSMC are well evaluated, and the switching losses of the 2L-HB merely amounts to 0.2%. Experimental validations were carried out for the HSMCs under various typical operating conditions. The measured results verify the expected performance of the HSMCs in both the steady and dynamic states, confirming the effectiveness of the proposed MPC-based control strategy.