Short circuit detection and driving control with no blanking time for high voltage high power insulated gate bipolar transistors

Insulated gate bipolar transistors (IGBT) short-circuit (SC) protection is one of the most important protection methods for IGBT converter equipment. The fast detection and protection response time could reduce the permanent damage of devices, and extend their use life cycle. At present, the collector emitter voltage v ce desaturation method is widely used in the commercial IGBT drive circuit, which has blanking time of fault detection and protection. In this paper, an improved adaptive v ce SC detection and protection is proposed to realize the blanking time adjustment under different SC conditions. By the determination of the d i /d t characteristics of the current variation on the parasitic inductance between the power emitter and the Kelvin emitter of IGBT modules, the execution time of the two detection methods can be set. According to the switch process and the SC type, the corresponding logic processing will be carried out to realize the fast detection of different SC conditions. The circuit scheme without blanking time detection and protection is designed, and the circuit is modelled and simulated by Pspice. The IGBT driving circuit SC test without blanking time detection and soft turn-off protection has been carried out. Simulation and test results can verify the feasibility of the proposed circuit.


INTRODUCTION
Insulated gate bipolar transistors (IGBTs) used in many high power industrial applications need to be protected from over-current and short-circuit failures under external fault conditions. Such faults mostly result from the occurrence of an abrupt variation or short circuit at the load end. To improve the reliability of IGBTs, there are multiple protection approaches designed in modern power electronics systems, including over-voltage, over-current and over-temperature protection.
In particular, short-circuit protection is the most important among the existing protection technologies. Especially, IGBTs could withstand the short-circuit condition in less than 10 µs. Shortening the short-circuit detection and protection time can reduce the short-circuit fault's damage, and prolong the useful life of the IGBTs. The electrical parameters such as the gate voltage v ge , the collector voltage v ce and the collector current i c will change significantly under the short-circuit failures. In this way, various approaches have been proposed and studied to protect IGBTs [1]. For example, in [2] the authors use a printed circuit board (PCB) Rogowski coil to detect short circuits. In [3], the current sensing IGBT is used with a sense resistor, and the protection circuit detects the voltage drop of the resistor to measure the main IGBT current and protects the IGBTs from short-circuit faults. In [4] and [5], the technique using the induced voltage across the stray inductance between the Kelvin emitter (E) and power emitter (PE) terminal responds fast without taking various short-circuit faults into account. Due to the Miller effect, the waveforms of gate voltage under the normal and fault conditions are different. Thus, a fault-detection circuit using the IGBT gate-voltage pattern at turn-on transient has been proposed in [6][7][8]. Zeng et al. [9] proposed a global and real-time control with embedded hardware artificial neural network for imbalance current suppression. Wuest et al. [10] realized the turn-off delay control through parameter condition monitoring. Wang et al. [11] proposed a self-adaptive active gate driver to further optimize IGBT switching performance. Guo et al. [12] proposed a three-level gate driving method to increase IGBT's damping to suppress the inrush current and improve the inrush energy loss distribution. The de-saturation technique detects the collector voltage v ce under short-circuit faults, which is widely used in modern gate drivers [13,14]. Chen et al. [15] proposed an improved IGBT short-circuit protection method with self-adaptive blanking circuit based on v ce measurement, by feeding back the required minimum blanking time interval, which is decided by comparing v ce with the de-saturation reference voltage. The short-circuit faults are detected by combination of di/dt detection and v ce detection, which ensures the rapid and right responses [16]. Silicon-carbide (SiC) MOSFET modules exhibit narrow short-circuit withstand times and generally much lower short-circuit robustness than silicon (Si) IGBTs. Therefore, fast-and-reliable detection mechanisms are absolute necessities for SiC MOSFET modules. There are some improved detection methods for high-voltage high-power MOSFET in [17][18][19].
Considering the shortcomings of existing short-circuit detection methods, a short-circuit detection method without blanking time is presented in this paper to reduce short-circuit protection delay time and make the detection circuit suitable for different types of IGBT modules. It is based on the idea of using a combination of self-adaptive v ce detection and di/dt detection. The elimination of the blanking time is realized by using a complex programmable logic device (CPLD) to make logical judgement under different operation conditions. This paper is organized as follows: Section II introduces the state of arts of IGBT short-circuit faults detection. Section III analyses the short-circuit faults detection circuit without blanking time in detail. Section IV provides the simulation and experimental results, and the conclusions are given in Section V.

IGBT SHORT-CIRCUIT BEHAVIOUR AND DETECTION
The short-circuit characteristics of IGBTs reflect the ability to withstand fault current, including the magnitude and duration of short-circuit current. However, the short-circuit characteristics and robustness of different types of IGBT modules are uncertain under different short-circuit fault conditions. Therefore, it is necessary to adopt corresponding detection methods for different short-circuit faults [20].

Analysis of the short-circuit faults
Short-circuit fault test for IGBT T DUT junction temperature T j also has an impact on the short-circuit characteristics. T j is usually lower than the maximum junction temperature T vj in datasheet under normal conditions. The short-circuit current and the short-circuit duration decrease with the increase of the junction temperature T j when the gate voltage v ge and V DC can be controlled to a certain value. Moreover, T j rises rapidly under the short-circuit fault because of the high short-circuit energy loss. And the IGBT self-heating effect would also impose strong impacts on the IGBT's shortcircuit characteristics [21]. In addition, the structure design and processing technique also determine the short-circuit characteristics. MOS channel in IGBT structure affects turn-off loss E off and on-state voltage drop V CE(sat) . The wider the MOS channel, the larger the E off and the lower the V CE(sat) . The device with a wide MOS channel will withstand the high short-circuit current, which requires the fast fault detection and protection time.
IGBT short-circuit modes can be classified into two scenarios according to fault conditions [22]. Short-circuit I (hard switching fault, HSF) is a direct turn-on of the IGBT under shortcircuit conditions. And short-circuit II (fault under load, FUL) is the occurrence of short circuit during the on-state of the IGBT, which is a peak power-wise condition harder than that of HSF. Furthermore, in all typical IGBT applications, there are anti-parallel diodes in the IGBT modules. If a short-circuit fault occurs at the freewheeling diode, the normal operation of the IGBT will be affected. Thus, the occurrence of a short-circuit fault across the loading during the conducting mode of the freewheeling diode is denoted as short-circuit III (fault under freewheeling, FUF) [23].
As shown in Figure 1, the IGBT dynamic test circuit could be used to test the short-circuit characteristics of the bottom tube T DUT in half-bridge circuit. For either HSF or FUL, the short-circuit loop contains only circuit parasitic inductors and excludes the huge load inductor. Thus the copper bars or cables are usually used to replace the load inductance to simulate the HSF or FUL in the experiments. Typical HSF waveforms are given in Figure 2(a). In this mode, the IGBT is off and the bus voltage V DC is supported across the device during the prefault stage. The rate at which the device begins to conduct current is related to the charging rate of the Miller capacitance C gc . And dv ce /dt and C gc are much lower at higher voltage. So the displacement current i gc through C gc is small and hardly causes a change to v ge . When the device is gated on, v ge reaches gate-threshold voltage V ge(th) and i c begins to rise very quickly. And short-circuit current depends on the applied v ge and turn-on gate resistor. A notch is gouged out of v ce due to the voltage drops occurring across the parasitic inductance of the circuit.
The device might be subjected to a short-circuit fault in normal conduction. The waveforms in Figure 2 Initially the IGBT is operating normally, carrying a stable load current within its ratings. And v ce falls to a low voltage drop, which is generally 2-4 V. During FUL, i c rapidly rises up to its saturation level which depends on the gate-drive voltage, pulling the IGBT out of its saturation state. As v ce is increasing to V DC during the short-circuit, the high dv ce /dt can induce i gc through C gc . And the Miller effect has much more influence on FUL, particularly because C gc is very high at a low voltage. Hence, v ge sets higher and could cause an increase in the short-circuit current magnitude. In short, FUL could result in much higher fault current than HSF.
The waveforms of FUF is shown in Figure 2(c). FUF is the occurrence of short circuit across the load during the conducting mode of the freewheeling diode. Before the short-circuit, the IGBT is already turned on and its current is zero. At the same time, the inverse diode is conducting. If now the short circuit occurs at the load, the current is rapidly commutated from the diode to the IGBT, and the IGBT is passively turned into the short-circuit condition. Meanwhile, v ce increases to V DC while the IGBT transits to its de-saturation mode. The subsequent process is similar to the one seen in FUL. A dynamic shortcircuit peak current occurs because of an increase of v ge . When the short-circuit current falls to the fixed value, di c /dt affects the v ce peak value V peak . Since the drop rate of the short-circuit current cannot be controlled by v ge , the V peak is higher than the one during the soft turn-off process. FUL is more severe than HSF in practical applications due to the higher short-circuit current magnitude. Besides, HSF and FUL usually occur in the inverter circuits. FUF often occurs during the conducting mode of the freewheeling diode, such as the traction converters where the motor is used as generator.

Short-circuit fault detection methods
Many schemes have been discussed over the last few years for detecting the IGBT's short-circuit fault conditions. According to the sampling signal from the IGBT module, existing detection methods can be divided into four types-the collector voltage v ce , the gate voltage v ge , the collector current i c and the collector current rate di/dt. At present, the most common and typical solution is to monitor the change of v ce and di/dt. As shown in Figure 3, in terms of the high-power IGBT modules, there is a fixed parasitic inductor L PE-E between the power emitter (PE) and Kelvin emitter (E) terminals, which is generally less than 10 nH. In the case of constant L PE-E under switching operation, di/dt can be extracted by the induced voltage v PE-E across L PE-E . Note that during the short-circuit period, i c rises very quickly so that di/dt can be used as a short-circuit indicator. As a result, v PE-E induced by the short-circuit event can be contrasted with normal v PE-E for fault detection, which is shown in Equation (1).
The di/dt detection has fast response time. But it does not take various short-circuit faults into account. Compared with FUL and FUF, the method is more effective for HSF because the di/dt change is much higher in that case.
Many commercial drivers with integrated v ce detection have a measuring circuit to detect the short-circuit fault. When the IGBT is turned on normally, v ce will fall to a low voltage drop from V DC , and i c will rise to the load current level. Once the short-circuit fault occurs, the IGBT will exit the saturation state according to the output characteristic curves and v ce will increase up to V DC . So it can be used to indirectly detect the short-circuit fault based on the change of v ce . As shown in Figure 4, the v ce detection approach can be divided into two types: active detection and passive detection.
The active detection method implemented with a series of high voltage diodes D 1 is plotted in Figure 4(a). When the IGBT is normally turned on, a current generated by the power supply V CC flows to the IGBT collector through the limiting resistors R 1 and R 2 . Thus, the v ce detection voltage v A can be expressed by where: V F is the total forward voltage drop of the high voltage diodes; V CE(sat) is the collector-emitter saturation voltage drop. On condition that R 1 is much smaller than R 2 , Equation (2) can be simplified as follows During the on-state operation, v A is lower than the desaturation reference voltage V REF , and the comparator outputs the low level signal. When short-circuit fault happens, the v ce would increase quickly. And the high voltage diodes are reversely Turn-on switching characteristic of IGBT cut off, and then the capacitor C 1 is charged by V CC across R 2 . Finally, the measured v A is charged to the value of V CC . Because V CC is higher than V REF , the comparator outputs the high level fault signal. The gate driver would perform the soft turn-off protection.
As plotted in Figure 4(b), working principle of the passive detection circuit is similar to that of the active detection circuit, which consists of a series of resistors R 1 and R 2 . When v ce is V DC , the current i R1 flowing through R 1 is controlled at 0.6-0.8 mA, and v A must be lower than V CC in the situation. The capacitor C 1 and resistor R 3 are used to set the blanking time. The diodes D 1 and D 2 form the voltage clamping circuit. R 1 and R 2 can be designed by The v ce detection is not enabled until v ce falls to the saturation voltage drop. Thus, the method can only detect the de-saturation phenomenon of the IGBT, and cannot correctly judge the repeated changes of v ce . Therefore, the prerequisite for enabling the v ce detection method is to ensure that the IGBT is already in the on state. Figure 5 shows the waveforms of v ce , i c and v ge .
In order to properly protect the IGBT modules under shortcircuit fault condition, certain time must be reserved to ensure that the IGBT is turned on normally. During the period, v ce detection circuit is disabled, which is denoted as blanking time.
During HSF, the v ce detection can only detect the fault condition after the blanking time, which will put the IGBT and human at risk.

ANALYSIS OF SHORT-CIRCUIT DETECTION AND PROTECTION WITHOUT BLANKING TIME
Based on the aforementioned analysis, the short-circuit detection scheme without blanking time (NBTD) consists of v ce detection method and di/dt detection method with the logic control strategy. As shown in Figure 6, the principle of the proposed detection method is as follows: before normal turn-on, the detection circuit is disabled. Once the IGBT is turned on, the di/dt detection is enabled immediately. And the v ce detection is disabled because v ce is higher than the V CE(sat) . If HSF occurs during the turn-on transient, the gate driver detects the fault by the di/dt detection circuit and takes the protection measures directly. And the v ce detection does not work in this condition. Otherwise, the v ce detection circuit is not enabled until the IGBT works normally in saturation state. Based on the above analysis, it is ensured that there is no blanking time in the whole operating process of the IGBT.
The waveforms of the proposed detection method are plotted in Figure 7 during the normal condition and short-circuit faults. The detailed working process is explained as follows.
During the off-period (T 0 -T 1 ), the IGBT is off because v ge is lower than the gate-threshold voltage V ge(th) . And v ce is always equal to V DC . When v ge reaches V ge(th) at time T 1 , v ce starts to fall to V CE(sat) from V DC . In the Miller plateau (T 2 -T 3 ), v ce decreases more quickly. In the stage (T 3 -T 4 ), v ce is lower than the v ce detection enable-threshold V REF2 . Finally, v ce is equal to , v ce is higher than V REF2 , the comparator unit (5) outputs the low-level signal. At the same time, the output signal of the power amplifier unit (2) changes from low level to high level, and the inversion unit (6) outputs the low-level signal. Then, the output of the trigger unit (7) remains at the low level. Therefore, the output of the AND gate unit (9) is low-level, and v ce detection is disabled at this time.
If the HSF occurs before time T 1 , the collector current i c rapidly increases, whose rate could reach several kA/µs. As shown in (1), the induced voltage v PE-E across the parasitic inductor L PE-E is a negative voltage, which is related to the rate of i c . In this condition, di/dt detection unit (3) outputs the highlevel signal. Because the output signal of the power amplifier unit (2) v out is high-level, the AND gate unit (4) and OR gate unit (10) both output the high-level signal. The R-pin input signal of the trigger unit (11) is low-level. According to the preset logic, the trigger unit (11) outputs the high-level fault signal, so that the control generator unit (1) will block the control pulse signal and control the reducing-v ge -and-soft-turn-off unit (12) to take short-circuit protection action.
If there is no short-circuit fault during the period (T 0 -T 3 ), then v ce is lower than V REF2 . And the output signal of the comparator unit (5) changes from low level to high level. At the moment, the power amplifier unit (2) outputs the high-level signal, and thus the inversion unit (6) outputs the low-level signal. Based on the preset logic, the output of the trigger unit (7) changes to low level. Therefore, the output signal of the AND gate unit (9) is consistent with that of the comparator unit (5), and v ce detection is enabled at this time. After time T 4 , the IGBT enters the saturation area.
If FUL occurs under the on-state condition, i c rapidly increases, pulling the IGBT out of its saturation state. And v ce starts to rise up to V DC quickly. Because the v ce detection faultthreshold V REF3 is higher than V REF2 , the output signal of the comparator unit (5) changes from low level to high level once v ce is higher than V REF3 . And the output signal of the trigger unit (7) remains at the high level. The output signal of the AND gate unit (9) is high-level, which is consistent with that of the comparator unit (8). Thus, the OR gate unit (10) outputs the high-level signal. And the R-pin input signal of the trigger unit (11) is low-level. On the basis of the preset logic, the trigger unit (11) outputs the high-level fault signal, so that the control generator unit (1) will block the control pulse signal and control the reducing-v ge -and-soft-turn-off unit (12) to take short-circuit protection action.

Simulation results
In order to verify the feasibility of the proposed detection circuit, simulation using Pspice is performed. Figure 8 shows  Table 1.
As mentioned in Section II, short-circuit faults of IGBTs can be classified in two scenarios: HSF and FUL. According to the characteristics, the parasitic inductance in the HSF mode is a little smaller than the one in the FUL mode. Thus, Switch S 1 is closed to simulate HSF before the IGBT is turned on, where L str2 is 30 nH. Similarly, S 1 is closed to simulate FUL when the IGBT is in the on state, where L str2 changes to 5 µH. Figure 9 shows the simulation waveforms under the HSF condition. In Figure 9(a), when v ge reaches the gate-threshold voltage, i c begins to rise rapidly and finally to the short-circuit current. And there is a notch in the v ce waveform. Figure 9(b) shows the fault detection logic simulation waveforms. When the IGBT is turned on, the increase of i c produces the inductive voltage v PE-E on L PE-E . When v PE-E is lower than V REF1 (=−7.5 V), the comparator output-signal out_1 changes to low level. And the di/dt detection-signal error_di/dt is high-level, so that the fault detection-signal error_sc changes to high level used to warn HSF. Because v ce does not drop to V CE(sat) , the v ce detection enable-signal enable_V CE remains at the low level, which indicates that the v ce detection is disabled. Then the v ce detection-signal error_V CE also remains at the low level. Similarly, Figure 10 shows the simulation waveforms under the FUL condition. In Figure 10(a), due to the increase of i c , the IGBT exits the saturation area. And v ce rises from the saturation voltage drop to V DC . Figure 10(b) shows the fault detection logic simulation waveforms. When v ge is higher than V ge(th) , i c rises slowly to the load current level, and v ce falls to V CE(sat) . Because the v ce detection voltage v A is lower than V REF2 , the output-signal out_2 changes to the high level. And the v ce detection enable-signal from trigger enable_V CE is highlevel, so that the v ce detection is enabled. During FUL, i c rapidly rises up and v ce also climbs up to V DC . Since v A is higher than V REF3 , the output-signal out_3 changes to the high level. And the v ce detection-signal error_V CE is high-level, so that the fault detection-signal error_sc changes to the high level used to warn FUL. The change of the collector current rate di/dt under FUL is much smaller than the one in HSF. Therefore, v PE-E is higher than V REF1 during FUL, so that the di/dt detectionsignal error_di/dt remains at the low level, which indicates the di/dt detection is disabled.

Simulated short-circuit tests
To analyse the feasibility of the proposed detection method, the simulated short-circuit tests are carried out. And the experimental results are shown in Figure 11. Based on the characteristics of the short-circuit faults, the induced voltage v PE-E is replaced with an adjustable DC voltage between the power emitter (PE) and Kelvin emitter (E) terminals of gate driver to simulate HSF. In the same way, the v ce detection voltage v A is replaced with a changing voltage signal to simulate FUL. In Figure 11(a), when the control signal PWM is high-level, v ge also changes to 15 V from −15 V, which enables the di/dt detection. Because v PE-E (=−10 V) is lower than the di/dt-detection threshold V REF1  Figure 11(b), when v ge remains 15 V and the measured voltage v A is lower than the enable-threshold V REF2 (=6.8 V), the v ce detection is enabled. When v A is higher than the fault-threshold V REF3 (=6.8 V), the detection circuit regards the fault as the FUL mode. Then the gate driver also performs the soft turn-off protection quickly. Then v ge falls to the intermediate voltage V st (=10 V) and holds for 2.5 µs and then shuts down. It can be seen from the simulation results and the simulated short-circuit test results that there is no blanking time during the whole detection process. The proposed detection method can quickly detect HSF and FUL, which greatly shortens the duration of the short-circuit fault.

Double pulse tests
In order to test the stability and rationality of the gate driver in the actual circuit, the double-pulse setup is used to carry out the double-pulse test (using Infineon IGBT module: FF450R33TE3). The test schematic and the setup are shown in Figure 12. In the double-pulse test, the relationship between the load current change △i c , the bus voltage V DC and load induc- tance L load can be expressed as The test is done under the bus voltage 1500 V and gateemitter voltage ±15 V in which the load inductance is 150 µH. In the double-pulse test, firstly a steady turn-off signal is given to the top device Q 1 and then a long turn-on pulse is applied to the bottom device Q 2 in Figure 12. And V DC is applied across the load inductor during this time interval, and therefore the collector current i c rises. The duration of this pulse is adjusted according to the required test current. Q 2 is turned off at the end of the first pulse. And i c free-wheels through the diode while the IGBT is off. After a short while, Q 2 is turned on again, and i c commutates from the free-wheeling diode to the IGBT. The Q 2 off time between these two pulses is kept short so that the change in inductor current is minor. Then Q 2 is turned off again after a small time interval, and i c flows through the diode until it gradually reduces to zero.
The double-pulse test waveforms for 1500 V and 450 A are shown in Figure 13. The device turn-off characteristics is obtained at the falling edge of the first pulse, and the turn-on characteristics is obtained at the rising edge of the second pulse. In Figure 13(a) the overall record during the double-pulse test is shown, while Figure 13(b) shows the turn-off transition and Figure 13(c) presents the turn-on transition. The width of the first pulse is set according to the rated current level, which is 450 A in this particular case. At the end of the first pulse, the IGBT turns off, and the peak overvoltage V peak is 2010 V, which does not exceed the breakdown voltage. After a short while, the IGBT is turned on again, and the maximum current I peak is 670 A, which is lower than the repetitive peak current.
According to the switching waveforms of the IGBT, both the turn-on and turn-off transitions are consistent with the actual application. And the gate driver can provide sufficient driving capacity to ensure the reliable operation of the IGBT, which fulfils the design requirements.

Short-circuit tests
In order to verify the effectiveness of the proposed detection method in the actual circuit, two kinds of short-circuit tests are Similarly, a stable turn-off signal is applied to the top device Q 1 in Figure 14. Considering that the IGBT can withstand the short-circuit condition for 10 µs, thus a single pulse (15 V, 15 µs) is applied to the bottom device Q 2 . Moreover, the copper bars and the small inductor 6 µH are usually used to replace the load inductance to simulate HSF and FUL in the experiments. Figure 15 shows the hard-switch-fault test waveforms using the homemade and domestic QD series gate drivers. In Figure 15(a), the control signal is changed from low level to high level and v ge begins to rise. After about 2 µs, v ge reaches V ge(th) and i c begins to rise quickly. At this time, v ce drops slightly and  v PE-E starts to decrease because of di/dt. After 1.8 µs, the measured v PE-E is lower than the di/dt-detection threshold V REF1 (=−7.5 V). And the detection circuit recognizes that the IGBT is under the HSF condition. Then the gate driver performs the soft two-level turn-off protection quickly. The v ge falls to the intermediate level and holds for 2.5 µs and then shuts down. As viewed from the waveforms, short-circuit detection and protection circuits work normally.
As shown in Figure 15(b), there is only the v ce detection in the domestic QD series gate drivers without soft turn-off protection. With the conventional method, the IGBT is turned off 5 µs after the short-circuit event. Compared with the proposed FIGURE 16 Fault under load test waveforms. (a) Homemade gate driver, (b) domestic QD series gate driver detection method, the protection time is longer and the peak overvoltage V peak is higher. Figure 16 shows the fault-under-load test waveforms using the homemade and domestic QD series gate drivers. The rising rate of the collector current di/dt under FUL is much lower than the one in HSF. Initially v ce falls to V CE(sat) from V DC , which enables the v ce detection. In Figure 16(a), as i c increases and reaches 1300 A, v ce starts to rise up to V DC . When the measured v A is higher than the v ce -detection threshold V REF3 (=6.8 V), the detection circuit recognizes that the IGBT is under the FUL condition. Then the gate driver also performs the soft two-level turn-off protection quickly. After about 5 µs, the IGBT exits the saturation state with an L load of 6 µH. Then the IGBT under the FUL is turned off 3 µs after the short-circuit event. During the soft turn-off protection process, i c gradually drops to twice the rated current, in which V peak is lower than the one when the IGBT is turned off.
As shown in Figure 16(b), the QD series gate drivers do not have the soft turn-off protection. When i c reaches 1150 A, the IGBT is pulled out of its saturation state. As i c continues to rise, the IGBT is turned off 1 µs after the short-circuit event. Without an intermediate level, the turn-off peak overvoltage V peak reaches 2500 V due to the higher turn-off current.
The performance of the homemade gate driver with the proposed detection method (NBTD-IDR) is compared with that of the domestic QD series gate driver (QDT-IDR) in Table 2. Different features confirm that the proposed detection method  is superior to the conventional v ce detection method. In HSF, compared with the QDT-IDR, the proposed detection method reduces the fault-detection time and peak overvoltage V peak to 1.8 µs and 2000 V, respectively. In FUL, compared with the QDT-IDR, the proposed detection method reduces the faultdetection time and peak overvoltage V peak to 5.0 µs and 2100 V, respectively. Moreover, Table 3 compares the proposed detection method with other conventional methods. The v ce detection method is quite cheap and easily implementable. However, it requires blanking time, which can prolong the short-circuit time. And the blanking time should be carefully designed for different types of IGBT modules, which increases the difficulty of driver design. The fault-detection time of the v ge detection method is short, but v ge is easily affected by parasitic parameters. Therefore, the detection circuit is complicated because of its extraordinary sensitivity, and has low reliability. The i c detection method using sense resistor or Rogowski coil is capable of measuring a very high di/dt with a short delay. However, it is susceptible to external electromagnetic interference and expensive to produce. The di/dt detection method responds fast with a low cost easy-tointegrate detection circuit. But it does not take various shortcircuit faults into account.
Based on the combination of v ce detection and di/dt detection, the proposed detection method can quickly detect the short-circuit faults with a minimum delay time, and flexibly adjust the fault-detection threshold voltages. The elimination of the blanking time is realized with the logic control strategy under different operation conditions. The di/dt detection method can detect HSF efficiently. For FUL, the v ce detection method is not enabled until v ce falls to V CE(sat) . Once v ce begins to increase during the on-state, the soft turn-off protection is performed by gate driver immediately. Moreover, the two-level turn-off protection can reduce the short-circuit current and loss to a relatively safe level, in which the peak overvoltage can be suppressed to a safe range. Compared with other conventional methods, the proposed method can also reduce the design complexity and cost of the detection circuit, and improve the reliability and applicability of gate driver.

CONCLUSIONS
In this paper, the short-circuit failure modes and mechanisms of the IGBT have been discussed in an effort to determine the detection circuits. Methods of fault detection have also been discussed. Their general advantages and disadvantages are pointed out so that an appropriate detection method may be selected. A short-circuit detection method without blanking time is presented for the IGBT gate driver. And its principle and implementation are discussed in detail. Afterward, the feasibility of the proposed short-circuit detection scheme is verified by the simulation results. Meanwhile, three different types of experiments are carried out: simulated short-circuit fault tests, double pulse tests and short-circuit tests. And the results show that the proposed circuit can detect short-circuit faults with a minimum delay time and perform the soft two-level turn-off protection quickly, which can shorten the short-circuit fault duration, reduce the short-circuit fault damage and prolong the useful life of the IGBTs. Moreover, it is suitable for the application on different kinds and working conditions of IGBT modules and the applicability of gate driver can be improved effectively.