Arm current reversal-based modular multilevel DC-DC converter

Nowadays, most of the converters used in high-power high-voltage (HV) applications are the conventional modular multilevel converters (MMC). However, in the case of DC-DC conversion, an imbalance of the capacitor voltages occurs and the conventional MMC fails to operate correctly. This paper introduces an arm current reversal-based modular multilevel DC-DC converter, which successfully provides balance among the capacitor voltages while operating in DC-DC conversion. The proposed conﬁguration is used in medium voltage DC grids to feed DC loads or to interconnect between two DC grids of different voltage levels. The proposed converter is a two-stage DC-DC modular converter, which consists of a single-phase half-bridge MMC with half-bridge submodules (HBMMC) followed by a single-phase H-bridge MMC with half-bridge submodules (SMs). The operational concept of the proposed converter is based on reversing the arm current direction and reversing the output terminals with the help of the H-bridge MMC stage, which ensures the same direction of the voltage at the load terminals. The proposed converter provides a high conversion ratio, bidirectional power ﬂow, simple architecture, and a simple control scheme. Detailed illustrations, analysis, and design of the proposed converter are presented. Besides, MATLAB-based and Opal RT-based simulation results and experimental results are presented to validate the proposed conﬁguration claims.

cations, the capacitors suffer from high-ripple voltage unless hardware/software solutions have been added to the converter or even bulky capacitors have been used. In the case of the DC-DC conversion process, energy drift occurs between the upper and lower arms of the conventional MMC due to the unipolar arm currents, which results in operating with unbalanced capacitor voltages [7].
In the literature, different approaches based on hardware/software modifications have been presented to overcome the capacitor voltage imbalance issue during the DC-DC conversion process. One of the software-based approaches is the injection of the AC circulating current to the conventional MMC, where it allows charging and discharging of the arm capacitors. Hence, a successful DC-DC conversion is achieved. However, an optimization technique should be applied on the injecting current as presented in [8], because high circulating current leads to excessive current stresses on the involved IGBTs in addition to higher operational losses, which decreases the converter efficiency. On the other hand, special HBSMs-based modular DC-DC converter topologies with FIGURE 1 The architecture of the existing DC-DC converter presented in [21] cross-connected capacitances [9] and cross-connected arms [10] were presented in the literature. In these topologies, to ensure the operation with balanced capacitor voltages, an AC voltage injection is used. The number of switches in these configurations is relatively high. A similar concept with HBSMs as well as FBSMs has been proposed for bipolar DC systems in [11]. Some researchers suggested employing the conventional MMC in DC-DC operation with an additional hardware circuit, which is named energy equalizing modules (EEMs) [12][13][14][15][16]. The EEMs ensure arms energy balance where balanced capacitor voltages are achieved. Using EEMs needs many semiconductor devices, EEMs controllers, and transformers, which increases system complexity and cost. Alternatively, hybrid modular DC-DC converters that use high-voltage valve(s) in addition to HBSMs and/or FBSMs are proposed in the literature [17][18][19][20]. The highvoltage valve in these converters consists of a series-connection of IGBTs and is operated under zero-voltage switching.
Recently, a modular DC-DC converter, which is based on the arm interchange concept, was proposed in the literature [21], where the upper and lower arms are exchanging their positions during operation to ensure balanced capacitor voltages in DC-DC conversion. This presented topology is comprised of a twostage modular DC-DC converter. The first stage consists of a half-bridge single phase MMC with HBSMs while the second stage consists of an H-bridge single phase MMC with FBSMs as shown in Figure 1. Therefore, it has a relatively complex architecture and control scheme.
In this paper, an arm current reversal-based modular DC-DC converter is presented, which successfully achieves bal- The first stage is a half-bridge single-phase HBSM-based MMC (HBMMC), while the second stage is an H-bridge single-phase HBSM-based MMC. The first stage generates the required output voltage, but only in half of a predetermined periodic time and its negative value in the other half. The capacitors are charging in only half of the periodic time and are discharging in the other half, because the arm current is reversed, that is, operating with bipolar arm currents. The second stage is the rectification stage, where it is controlled, such that its output is the required DC voltage for the whole period. Hence, a successful DC-DC conversion with balanced capacitor voltages is achieved by employing the proposed arm current reversal concept. The proposed DC-DC converter shown in Figure 2 may fit in mediumvoltage medium power applications as single leg-based MMC with relatively bulky DC-link capacitances is employed, where the size of capacitors increases with the increase of converter power rating. For the proposed converter to be used in high voltage high power applications, the first stage is replaced by an H-bridge MMC instead of the half-bridge MMC as shown in Figure 3.
The detailed operational concept of the arm current reversalbased modular DC-DC converter is presented along with capacitor voltage ripples analysis and passive components design. To clarify the proposed approach's pros and cons, a comparison has been made between the proposed topology and other different topologies of modular DC-DC converters in the literature. The main contributions of the presented approach can be summarized as follows.
• The arm current reversal-based modular DC-DC converter is proposed where a successful DC-DC operation with balanced capacitor voltages has been realized. • The proposed configuration provides a bidirectional power flow, high conversion ratio, low current stresses, low number of IGBTs, simple architecture, and simple control scheme.

THE PROPOSED CONFIGURATION
To overcome the challenge of the SMs capacitor voltages unbalances in conventional MMCs in the case of DC-DC operation, a new arm current reversal-based modular multilevel DC-DC converter is proposed. In the proposed configuration, there is no need for injecting high AC circulating current nor using special modular topologies.
The main concept of this configuration is the inversion of the arm current direction while keeping the output current unchanged.
The proposed configuration is a two-stage modular DC-DC converter, which comprises a half-bridge single-phase MMC with half-bridge SMs (HBSMs) followed by an H-bridge singlephase MMC with HBSMs connected to its output as illustrated in Figure 2. In the first stage, the output voltage of the HBMMC is controlled, such that it generates the desired output voltage (V o ) only in half of a predetermined periodic swapping time (T b ), which can be named, the positive half cycle. While the HBMMC generates the negative value of the desired output voltage (−V o ) in the other half, which can be named, the negative half cycle. In the second stage, in the positive half cycle, the SMs of the H-bridge arms F1 and F2 will be deactivated, which acts as a short circuit, while the other arms R1 and R2 will have their SMs activated. Alternatively, in the negative half cycle, the situation is reversed, where the two arms' SMs R1 and R2 will be deactivated, while the arms F1 and F2 will have their SMs turned on producing the same desired output voltage during the whole period as shown in Figure 4.
In other words, as seen in Figure 5, in the positive half cycle, the number of activated SMs in the lower arm of HBMMC is larger than that of the upper arm hence, the lower SMs capacitors are discharging, while the upper SMs capacitors are charging. Nevertheless, in the negative half cycle, the number of activated SMs in the upper arm is larger than that of the lower arm leading to the arm currents reversal, so the upper SMs capacitors are discharging while the lower SMs capacitors are charging. However, the same output DC voltage is maintained in the whole period thanks to the H-bridge MMC. By continuous swapping between the positive and negative cycles with proper swapping periodic time (T b ), low ripple voltage in the capacitors is achieved.
It has to be noted that the number of submodules in each arm of the HBMMC stage is N, while the number of submodules in each arm of the H-bridge MMC is N/2, where the output voltage of the HBMMC ranges from −V dc /2 to V dc /2. Any modulation technique can be used to extract the number of SMs to be activated in each arm for the given arm reference voltages. In this paper, the employed modulation technique is  [22] and a conventional voltage-balancing algorithm is applied [23]. It is worth noting that the voltage conversion ratio (V o /V i ) of the proposed DC-DC converter ranges from 0.5 down to 0 without any restrictions, it is simply changed by modifying the reference output voltage.

Modelling
The simplified MMC model with equivalent capacitors presented in [24] is used in this work to study the dynamic performance of the proposed modular multilevel DC-DC converter. The equivalent circuit of the proposed approach is shown in Figure 6. This simplified model replaces the series-connected submodules with an equivalent capacitor, whose capacitance depends on the number of connected submodules. The C u and C l in Figure 6 represent the equivalent capacitances in the upper and lower arms respectively, which are defined in Equations (1) and (2), where C is the nominal capacitance of the SMs capacitors in the HBMMC, while u and l are the number of activated submodules in the upper and lower arms respectively.
The number of activated SMs in the upper and lower arms of HBMMC is defined in Equations (3) and (4) respectively as a function of the output voltage modulating signal (v m ), which is Based on Figure 6, assuming no arm inductance (L a = 0), the upper and lower arm currents are given by; where (I b ) is the output current of the HBMMC stage, substituting Equations (3) and (4) into Equations (5) and (6), the arm currents will be The modulating signal (v m ) in the proposed DC-DC converter is defined by; where V o is the desired DC output voltage level.

HBMMC capacitor voltage ripple calculation
The change in the voltage of each submodule capacitor in the upper and lower arms of HBMMC is given by; By substituting Equations (7) and (8) into Equations (10) and (11), the change in the capacitor voltage in upper and lower arms are expressed by Equations (12) and (13) respectively.
Taking into consideration that (v m ) is a DC value in both halves of the periodic time, then the change in the upper and lower capacitor voltages can be calculated as follows.
Assuming a smoothing reactor (low-pass filter) is used at the load terminals, then the half-bridge MMC (HBMMC) output current (I b ) can be defined as (16) where (I o ) is the DC load current. Taking into consideration (v m ) mentioned in Equation (9), the corresponding change in the capacitor voltage in the upper arm is given by Similarly, for the change in the lower arm capacitor voltages. Finally, the capacitor voltage ripple is given by: Based on Equation (19), it must be noted that the ripple voltage in the capacitors decreases with decreasing the swapping time (T b ) and/or decreasing the output current (I o ).

DC-link capacitors voltage ripple calculation
By applying Fourier analysis for the bridge current I b (t) given by Equation (16), the fundamental component of the current I b (t) is given by: The fundamental component of the DC-link capacitor current (I CF ) is half of I b1 (t).
The peak-to-peak voltage ripple of the DC-link capacitors due to the current I CF , namely, V r p-p is given by Equations (22) and (23), where I CF pk and X c are the peak of the capacitor fundamental current and fundamental capacitive reactance of DC-link capacitor respectively.
where C s is the capacitance of the DC-link capacitors. Since the converter output power (P o ) is equal to V o × I o , the ripple voltage V r p-p can be written as a function of the converter output power as follows.

Losses calculations of the proposed converter
To estimate the losses in the proposed converter, both the conduction and the switching losses of both stages of the proposed converter should be calculated. Assume that each IGBT/diode has an on-state voltage (V on ) and on-state resistance (R on ). Also, each IGBT has a turning on time (t on ) and a turning off time (t off ).
Regarding the conduction losses of the first stage (HBMMC), by substituting Equations (16) and (9) in Equation (7), the upper arm current is given by: Then the conduction losses of each switch in the upper arm can be given by: where |I arm u 1 avg | and |I arm u 2 avg | are the absolutes of the average upper arm current in the first and second half-cycles, respectively, while I arm u 1 rms and I arm u 2 rms are the RMS values of the upper arm current in the first and second half-cycles, respectively. Since one semiconductor is conducting per SM at any instance and each arm consists of N SMs, then the conduction losses of the first stage (HBMMC) can be estimated as follows; (27) Alternatively, for calculation of the switching losses of the HBMMC stage, the switching losses of each IGBT can be calculated as follows; Since there are two switches in each SM, if the current passes through the IGBT of one of the switches before the switching instance, then after it the current passes through the diode of the other switch and vice versa. Therefore, for switching losses calculations, only one IGBT per SM is considered. The switching losses of the HBMMC stage can be calculated as follows, taking into consideration that HBMMC consists of two arms and each arm comprises N SMs On the other hand, regarding the conduction losses of the second stage (H-bridge MMC) and because the output current passes in each arm for only half of the periodic time, then the conduction losses of each switch can be calculated as follows: Since the second stage consists of four arms where each arm consists of N/2 SMs then the conduction losses of the second stage can be estimated as follows: Regarding the switching losses of the H-bridge MMC, the switching losses of each IGBT can be given by; where f b is the switching frequency of the IGBT in the second stage that equals (1/T b ). Therefore, the switching losses of the H-bridge stage can be calculated as follows;

Numerical example
For the proposed DC-DC converter with V dc = 10 kV, T b = 0.01 s, N = 4, and V o = 0.25 × V dc = 2.5 kV. Based on Equation (19), the capacitor voltage ripple of HBMMC capacitances is given by Equations (34) and (35). Figure 7 shows the corresponding 3D plot of the voltage ripple percentage of the HBMMC capacitors with the output current and the HBMMC SMs capacitance for the given numerical example.
Similarly, based on Equation (24), the DC-link capacitor voltage ripple is given by Equations (36) and (37), where Figure 8 shows the 3D plot of the percentage peak-to-peak voltage ripple of the DC-link capacitors versus the output power and the DC-link capacitance.
Assuming the proposed converter is delivering a power of 400 kW, where V on = 2 V and R on = 1 mΩ, while the sum of t on and t off equals 1 μS, with a switching frequency of 2000 Hz, then the conduction and the switching losses of the first stage can be calculated according to Equations (27) and (29) to be 1.7 and 2 kW, respectively. Also, the conduction and the switching losses of the second stage are calculated according to Equations (31) and (32) to be 1.7 kW and 100 W respectively. Finally, the efficiency is found to be 98.9%.
The switching losses of the second stage MMC are very low due to the low switching frequency of the second stage.

Limitations of the proposed converter
The limitations of the proposed topology are as follows: • The output voltage of the proposed converter is limited to only half of the input voltage (0.5V dc ). • The power level of the proposed converter is limited by the size of required DC-link capacitors, as the capacitor size increases with the increase of the converter power level (i.e. bulky DC-link capacitors are needed in high power levels).
These limitations can be avoided by upgrading the converter to the H-bridge front-end converter (i.e. employing two legs instead of one leg HBMMC as a front-end converter) as seen in Figure 3

Comparison between the presented approach and other existing modular DC-DC approaches
In this subsection, a comparison has been held between the presented converter and other modular DC-DC converters that exist in the literature [9,10,21], assuming few MW power rating and 10 kV/2 kV conversion ratio as shown in Table 1.
Based on Table 1, the proposed converter and the converter presented in [21] have nearly the same concept. However, the proposed converter has a lower number of IGBTs and arm inductors, and a single type of SMs (only HBSMs) are used, hence more simple architecture and control scheme.

SMs capacitance of the HBMMC
With the help of Equation (19), based on the desired SMs capacitor voltage ripple for the given output current level, dc-link voltage level (V dc ), and swapping time (T b ), the proper SM capacitance of the front-end HBMMC can be estimated.

DC-link capacitors (C s )
With the help of Equation (24), based on the desired voltage ripple of the involved DC-link capacitors for the given output power level, output voltage level (V o ), and swapping time (T b ), the proper capacitance of DC-link capacitors of the front-end HBMMC can be estimated.

Arm inductor (L a )
The arm inductor is chosen to satisfy fast steady-state condition after switching from the positive half cycle to the negative half cycle and vice versa. To achieve that, the natural response's peri-

Output L-filter (L f )
An output L-filter is connected in series at the output terminals of the converter to ensure a smooth current. To have a smooth output DC current (I o ), the L-filter inductance is chosen, such  (39), where τ is defined as the filter inductance (L f ) divided by the load resistance (R Load ).

SMs capacitors of the H-bridge MMC (C b )
The capacitances of H-bridge MMC at the output stage are chosen to ensure that the output voltage is divided equally among the activated H-bridge MMC SMs, hence no bulky capacitors are needed, i.e. they are used as snubber circuits to clamp the module voltage, not to store the energy to be delivered to the load, which means small capacitances in range of picofarad are sufficient in this stage.

5.6
The swapping period (T b ) As (T b ) is decreased at a given peak to peak capacitor voltage ripples, the submodules' capacitance, as well as the DC link  capacitance, decrease, but the switching losses are increased. Therefore, the selection of T b is based on compromising between the losses in the H-bridge MMC SMs switches and the capacitor size of both the HBMMC SMs and the DC link.

SIMULATION
A simulation model has been built for the proposed modular DC-DC converter using both MATLAB/SIMULINK software package and OPAL-RT (OP4510), which is a real-time digital simulator, with a conversion ratio of 5:1 assuming the parameters listed in Table 2. It is worth noting that for V dc = 10 kV, V o = 2 kV, T b = 0.01 s, and peak to peak ripple voltage < 2%, Based on Equation (19), the suitable capacitance of the HBMMC SMs should be higher than 4.2 mF, so 5 mF is chosen. Similarly, based on Equation (24) the required DClink capacitors should be higher than 4 mF, so 5 mF is selected. However, in the case of the H-bridge MMC SMs, a capacitance of 10 pF is chosen. Based on Equation (38), the corresponding arm inductance (L a ) should be much less than 0.5 mH. To ensure that and to decrease the L a di/dt effect, an inductance of 10 μH is chosen. Finally, based on Equation (39), the output filter inductance (L f ) should be higher than 25 mH hence 30 mH is chosen. A carrier frequency of 2 kHz and 0.5 kHz are employed for MATLAB/SIMULINK and OPAL-RT, respectively.
To show the viability of the proposed converter, two cases are considered. In the first case, namely, case 1; a passive DC load is assumed, while in the second case, a DC-link voltage of 2 kV is assumed at the low-voltage side to show the performance of the proposed approach as a DC transformer in DC grids. The cases are presented in detail in the following subsections.

Case 1: Passive DC load
In this case, a DC load resistance of 10 Ω is considered at the low-voltage side of the converter, while an output L-filter of 30 mH is connected in series with the DC load to ensure a smooth load current. In this case, open-loop control is used for simplicity, where the magnitude of the reference output voltage |V* o | is fed to the controller where the reference voltage is compared with multiple carriers using PSC-PWM, and the arm current reversal concept is applied as shown in Figure 9, such that it generates the gate pulses to the involved IGBTs. It has to be noted that the results of both MAT-LAB/SIMULINK and OPAL-RT are nearly identical. Figure 10(a) and (b) shows the output voltage at the low-voltage side (V o ) in the case of MATLAB and OPAL-RT respectively, where a successful generation of 2 kV average voltage is realized, hence, achieving a successful DC-DC conversion with a bucking conversion ratio of 5:1. Figure 10(c) and (d) shows the load current in the low-voltage side in the case of MATLAB and OPAL-RT respectively, where a load current of 200 A is generated successfully. Figure 11(a) and (b) shows the HBMMC capacitor voltages in the case of MATLAB and OPAL-RT respectively, where the state of the capacitor voltage changes from charging to discharging and vice versa because of the swapping between the positive and negative cycles with T b = 0.01 s. This results in balanced capacitor voltages with peak-peak ripple voltages of 42 V (1.68%), i.e. less than the defined 2% ripple voltage. Figure 12(a) shows the DC-link  Figure 12(b) shows the corresponding HBMMC arm currents, where the arm currents are limited, hence, low current stress operation. Figure 12(c) and (d) shows the H-bridge input voltage and current respectively. The direction of the bridge input voltage and current is reversed in every swapping time, i.e. the arm current reversal concept is applied successfully. The voltages of the H-bridge arms are depicted in Figure 13(a). To show the arm current reversal concept effectiveness, the proposed arm current reversal control is disabled and then enabled. Corresponding to this action, the voltages of the HBMMC SMs capacitors are depicted in Figure 13(b), where the capacitor voltages diverge at the instant of disabling the proposed control then converge again at the instant of enabling it.

Case 2: DC transformer
The presented modular DC-DC converter in this case is used as a DC transformer, which connects two DC grids of different voltage levels. The high-voltage side is named (V dc ), while the low-voltage side is named (V DCL ). As mentioned earlier, the proposed converter configuration allows a bidirectional power flow between the high and the low voltage sides. In this case, closed-loop control is used. By controlling the low voltage side current (i o ), the direction of power transfer is determined. The reference value of the low voltage side current (i* o ) is compared with the actual value, and the comparator output error is fed to a proportional-integral (PI) controller to provide the proper output voltage reference magnitude |V* o |. Then the employed controller generates the suitable gate pulses to the involved switching devices. If the reference current (i* o ) is positive, then the power flows from the high-voltage side to the lowvoltage side. However, if the reference current (i* o ) is negative, the power direction is reversed. To clarify the proposed converter capability of bidirectional power flow, a simulation model has been constructed on OPAL-RT, where the corresponding results are shown in Figure 14, where the output current reference (i* o ) is changed gradually from 200 A to −200 A with the same defined parameters in Table 2. Figure 14(a) and (b) shows the output current and the input current at the V dc side respectively, where their direction is reversed successfully at the same time. It is worth mentioning that if the output voltage of the converter is higher than the V DCL , the output current is in the positive direction and the power flows from the high to the low voltage side. However, if the output voltage is lower than the V DCL then the situation is reversed where the output current is in the negative direction and the power flows from the low to the high voltage side. To show the performance of the presented modular DC-DC converter during a DC-fault. A DC-fault has been introduced to the low-voltage side (V DCL = 0), while a 10 kV source is connected to the input terminals of the high-voltage side. The fault has been simulated at t = 1 s and the gate pulses of all involved switching devices are inhibited after fault detection. The currents at both the low and high voltage sides during the low voltage fault are depicted in Figure 15(a), where both currents decrease to zero without any inrush currents. Hence no need for a circuit breaker at the low voltage side. Figure 15(b) shows the DC link capacitor voltages, which remain almost around their nominal values. The arm currents in the HBMMC decrease to zero, as depicted in Figure 15(c), without any high circulating currents at the instant of the low-voltage fault. The HBMMC capacitor voltages decay slowly as shown in Figure 15(d) due to the parasitic resistance of the converter.
It has to be noted that when the fault is applied to the highvoltage side (V dc = 0), while a 2 kV source is connected to the terminals of the low-voltage side, the DC-link capacitors discharge through the fault and resulting in a high inrush current. In addition, after the DC-link capacitors are fully discharged, the series filtering inductance at the high side forces that high current to flow through the arm diodes of the HBMMC. Therefore, a DC circuit breaker is needed at the high voltage side to interrupt the flow of high discharge current due to the dc-side fault at the high-voltage side.

EXPERIMENTAL VALIDATION
A small prototype of the presented arm current reversal-based modular DC-DC converter has been implemented, as depicted in Figure 16 with the parameters given in Table 3. For simplicity, the H-bridge MMC is replaced by an H-bridge inverter with 4 IGBTs. Besides, a sensor-less system is used with the PSC-PWM modulation technique. To validate the proposed configuration, an open-loop control approach has been employed, where the reference output voltage magnitude is defined and fed to the controller to provide the suitable gate pulses to the involved switching devices. The corresponding experimental results for an output voltage reference of 0.25V dc , i.e. a bucking ratio of 4:1, are shown in Figures 17-20, where the DC output voltage is generated successfully with balanced capacitor voltages. Figure 17(a) and (b) show the output voltage and the output current, respectively, with the proposed arm current reversalbased modular DC-DC converter, where a DC output voltage is generated successfully. Figure 17(c) shows the HBMMC capacitor voltages in the upper and lower arms. The capacitor voltages in both arms charge and discharge in every period, therefore, remain balanced with acceptable voltage ripple. The input current at the V dc side is depicted in Figure 17(d). Figure 18(a) and (b) shows the internal upper and lower arm voltages of the HBMMC, respectively, while the arm currents in the HBMMC are shown in Figure 18(c) and (d), respectively, which are bipolar. Figure 19(a) and (b) shows the H-bridge input voltage and current respectively, which are the AC output values of the first stage (HBMMC) before being rectified by the second stage.
To show the experimental dynamic behaviour of the proposed DC-DC converter, a sudden increase in the load current is applied to the converter, where the output current is increased from 1.5 to 2.4 A. The corresponding results of the output and the input currents are depicted in Figure 20(a). Also, the corresponding arm currents are shown in Figure 20(b). Based on the presented experimental results, a DC-DC conversion is achieved successfully with balanced capacitor voltages. An efficiency of 83.5% is measured for the implemented low-voltage experimental setup.

CONCLUSION
In this paper, a new arm current reversal-based modular DC-DC converter is presented, which successfully achieves balanced capacitor voltages when operating in DC-DC conversion. The proposed configuration consists of a half-bridge single-phase DC-AC HBSM-based MMC (HBMMC) followed by an Hbridge single-phase AC-DC HBSM-based MMC. The HBMMC is responsible for generating the desired DC output voltage, but only in half of a predetermined period, and its negative value in the other half, where the arm current is reversed every half period. Hence, both the charging and discharging of the capacitors occur in each period. The generated voltage of the first stage is fed to the H-bridge MMC, which acts as a rectifier and generates the desired DC output voltage for the whole period. Therefore, a successful DC-DC conversion is achieved while maintaining balanced capacitor voltages by applying the proposed arm current reversal concept. Detailed illustration of the proposed concept, along with the voltage ripples analysis and passive components design are presented in this paper. The proposed approach provides high DC-DC conversion ratios, bidirectional power flow, low current stresses, and a low number of IGBTs. Finally, simulation and experimental results are demonstrated to confirm the validity of the proposed approach.