A non‐isolated DC‐DC converter with low voltage stress and high step‐down voltage conversion ratio

Correspondence Stylianos P. Syrigos, Laboratory of Electromechanical Energy Conversion, Department of Electrical and Computer Engineering, University of Patras, RionPatras 26504, Greece. Email: ssyrigos@ece.upatras.gr Abstract This work focuses on a new non-isolated interleaved DC-DC converter with very high step-down voltage conversion ratio. By employing the switched/series capacitor concept, along with the proper component interconnection, the converter features a high step-down voltage conversion ratio where, in the private case of equal duty ratios, it is six times higher than the conventional buck converter. This high step-down voltage conversion ratio is achieved with the lowest number of components compared to other similar topologies of the same conversion ratio. Also, due to the blocking/series capacitors, the voltage stress on the switches is reduced, improving the converter efficiency. One of the key features of the proposed converter is the inherent automatic current sharing between the interleaved phases, which in the case of equal duty ratios, is uniformly distributed. To add on, due to the use of only two interleaved phases, the converter has a wide output voltage range, since the duty cycle can be extended to 0.5. To validate the proposed converter operation, a 250 W wide-input/wide-output experimental prototype was built, achieving a peak efficiency of 94%.

These applications require converters with high output current capabilities, tightly regulated output voltage, and high efficiency. Numerous isolated topologies could fulfil the previous characteristics. However, isolated topologies have drawbacks such as slower response in transients due to the transformer large inductances, high cost due to the customized transformer design, as well as high voltage stress on the devices during switching transitions, due to the transformer leakage inductance [14].
In cases where isolation is not mandatory, the conventional interleaved buck converter (IBC) could be introduced as a solution, due to its simplicity in design and control [15]. However, the major drawback of the IBC is the low efficiency at low duty cycle values, due to the high current stress on the semiconductor devices. Also, since the switch voltage stress is equivalent to the input voltage, transistors and diodes with high breakdown voltage are selected, leading to extended conduction losses due to the high on-resistance (R DSon ) of MOSFETs and high forward voltage of diodes, respectively. To achieve high step-down voltage conversion ratios combined with high efficiency and high output current capabilities, several topologies and PWM techniques have been proposed [8,14,.
To extend the duty cycle of the conventional IBC, the quadratic buck converter was firstly introduced in [16][17][18]. This topology is a two-stage converter where the step-down voltage conversion ratio is a function of the square of the duty cycle (D 2 ). The major drawback of this topology is the high voltage stress on the active switching device, which depends on the duty cycle and is always higher than the input voltage. Thus, the efficiency of this topology is affected by the high switching losses on the transistor. The same voltage conversion ratio (D 2 ) can be achieved in the conventional buck converter with the implementation of the dual PWM control, as introduced in [8]. The only drawback of the dual PWM control is that the high frequency carrier must be multiple times higher than the low frequency carrier, making the control difficult with conventional microcontrollers. The delayed quadratic buck converter, introduced in [19], employs an additional inductor, offering higher step-down voltage conversion ratio but the voltage stress on the main switch remains the same as in the conventional quadratic buck. By adding a switched-capacitor cell in the quadratic buck the step-down ratio is increased, but at the cost of even higher voltage stress on the main switching device than in the quadratic buck [20]. An improved version of the quadratic topology is the double quadratic buck [21], implemented by clamping the neutral point of the input voltage to another quadratic buck. The transistor voltage stress is halved but still depends on the duty cycle values, making the selection of devices with lower breakdown voltage difficult. Extreme quadratic based conversion ratios are, also, achieved by the fourth-order converter in [22] but at the cost of very high voltage stress on the main switch, depending on the duty cycle values.
Similar to the IBC is the series capacitor (SC) buck converter proposed and revised in [23] and [24] respectively, while its optimal steady-state and transient mode control is studied in [25]. Although the voltage conversion ratio is D/2, one transistor is stressed with the input voltage, leading to the selection of transistors with higher breakdown voltage and higher R DSon . An alternative SC IBC converter with reduced switch voltage stress and continuous input current is presented in [26]. Although the continuous input current feature improves the power quality at the converter input, the step-down ratio is not as high as in the original SC IBC. The double series capacitor buck converter (DSCBC) in [27], offers improved voltage stepdown ratio (D/3) with low component count. However, for equal duty ratios, one inductor has twice the current value of the other, leading to asymmetrical magnetic component design and higher output ripple than the conventional two-phase IBC.
Improved step-down voltage conversion ratios could, also, be achieved by employing the switched-capacitor concept [14,28,29]. This concept is either employed as a front-end cell of capacitors and diodes [14] or as a multilevel/multistage converter, such as the converters in [28,29]. As multistage converters, the voltage gain depends exponentially [25] or is based on mathematical sequences [29] on the number of cascaded switched-capacitor structures. In both cases, however, the number of components needed for interleaved converters is very high, making the implementation of such converters impractical.
Great step-down conversion ratios can be also achieved with the hybrid high-ratio voltage step-down converters, by employing more than one of the concepts above. A hybrid of the quadratic and series capacitor concept, proposed in [30], offers a wide duty cycle range and improved efficiency due to lower voltage stress on the devices but at the cost of a significantly high number of components. However, the most renown hybrid case is the switched/series capacitor concept [31][32][33][34][35][36][37]. Based on this, an expandable four-phase interleaved voltage step-down converter with quadruple conversion ratio (D/4) and low switch voltage stress was presented in [31]. The main converter drawbacks are the narrow duty cycle range (D max = 0.25) and the high number of magnetic components. The same conversion ratio is achieved by the converter in [32], when D < 0.25. Again, this converter has duty cycle limitations, as for higher values, the converter operation differs, and the step-down capability is degraded. Based on the [32] topology, the converter in [33] has a lower number of components and operates in two or three phase mode but the conversion ratio is only D/3. A four-phase converter with quadruple conversion ratio and low capacitor count is reported in [34]. Contrary to the low number of capacitors is the high number of semiconductor switches needed for the converter implementation. This conversion ratio is, also, offered by the two-phase converter in [35], with only two output buck stages and wide duty ratio (D max = 0.5), at the cost of higher output voltage ripple. An attempt to achieve greater conversion ratio (D/6) was made in [36] and [37], by expanding the converter presented in [35]. Yet, the number of diodes and magnetic components increases, whereas the duty cycle value is limited to 0.33.
To further increase the voltage step-down conversion ratio, the coupled techniques are introduced [38][39][40][41][42][43][44][45][46][47][48]. Some advantages of coupled inductors converters are the turns ratio dependent voltage conversion ratio, the ability to create single-input multiple-output converters (SIMO) and the possible creation of ZVS/ZCS conditions by carefully utilizing the leakage inductance. An SIMO converter with ZVS was proposed in [38]. Despite the high voltage stress on the transistors, the converter offers high conversion ratio. However, as in most SIMO cases, the converter lacks control of its secondary output voltage value, since it depends on several parameters besides the converter duty ratio, such as the output inductance value, the load etc.
In the category of single-output coupled inductor converters, the converter in [39] does not achieve high step-down ratio and the input switch must have higher breakdown voltage as it blocks the input voltage, affecting the converter efficiency, despite the ZVS condition. ZVS condition has, also, the converter in [40] but the blocking voltage of the input switch and diode equals to the input voltage as well, leading to selection of transistors with high breakdown voltage and high R DSon . The converter in [41] and its improvement in [42], has very high conversion ratio, and the combination of lower switch voltage stress with ZVS, improves the overall converter efficiency. However, the step-down conversion ratio is significantly affected by the coupling coefficient of the coupled inductors.
Other converters are offering ZCS conditions, taking advantage of the leakage inductance values [43][44][45][46][47][48]. Based on [35], the converter in [43] offers ZCS and increased conversion ratio. However, the switch blocking voltage remains high, similar to the converter in [35]. High step-down conversion ratio with ZCS characteristics has, also, the converter in [44]. The drawbacks of this topology are the high number of magnetic components and the very small duty cycle range (D max < 0.25). Low component count and high conversion ratio, with ZCS condition, is achieved by [45]. The switch voltage stress, however, depends on the duty ratio and turns ratio, where for n < 1 values, becomes significantly greater than the input voltage. Despite the great step-down conversion ratio, the converter [46] has high switch voltage stress, which combined with the inherent converter gain sensitivity to the coupling factor, makes it not very suitable for high input voltage applications. The converter in [47] is based on the converter [27], offering higher conversion ratio values. Still, the asymmetry on the inductor currents remains an issue, causing higher output voltage ripple as the ripple of the inductor phased currents are not cancelling each other. Another converter with ZCS and a self-driver synchronous rectifier is the converter [48]. The step-down ratio, however, is not as high compared to other coupled inductor topologies.
In general, several coupled inductors topologies and configurations have been proposed, managing to extend the conversion ratio due to the dependence on coupled inductors turn ratio. However, the circuit and design complexity of coupled inductor converters are very high, due to the transformer construction and additional conduction states related to the leakage inductance. Leakage inductance is a double-edged sword: on the one hand offers ZVS and ZCS conditions but on the other hand affects the step-down conversion ratio and if not properly addressed, it can create voltage overshoots with devastating effects for the semiconductor switches [49].
In this paper, an interleaved high step-down voltage conversion ratio converter is presented, with six times higher voltage conversion ratio than the conventional IBC (D/6). The converter is a hybrid topology which combines the switched and series capacitor structures as the front-end and the interleaved buck converter concept as the back-end, and has the lowest number of components, compared to similar topologies of the same conversion ratio. What is more, the appropriate front-end switched/series capacitor structure allows for low switch voltage stress during steady-state, and with the appropriate PWM sequence, offers automatic current sharing to its only two output inductors as well as a wide output voltage range due to the extended duty ratio limit, up to 0.5.
The operating principles of the converter are described in detail in Section 2. In Section 3, the dc voltage gain is extracted, and the automatic current sharing mechanism is explained. A converter design guide is presented in Section 4 and a comparison with other topologies of the same voltage conversion ratio is conducted in Section 5, highlighting the pros and cons of the proposed topology. A more practical approach to the component selection, as well as the most significant experimental results and power loss distribution, are presented in Section 6. Finally, conclusions are presented in Section 7.

OPERATING PRINCIPLES OF THE CONVERTER
The topology under investigation, shown in Figure 1, consists of six transistors, six blocking capacitors but only two inductors with their corresponding freewheeling diodes. The converter uses the blocking and series capacitor concept; by series charging and parallel discharging, the capacitors manage to divide the input voltage V in , automatically distribute the output current to the output inductors and increase the voltage conversion ratio.
Although the converter has a high number of switches, the operation is simple since only two PWM signals with 180 • phase-shift are needed. First, the group of transistors Q 1a , Q 1b and Q 1c is switched-on, and with 180 • phase-shift, the second group of transistors (Q 2a , Q 2b and Q 2c ) is switched-on. Due to the parallel discharging of capacitors, the maximum theoretical permitted duty ratio for each group is 0.5, since for higher duty ratios the converter will not operate in the intended mode. Nevertheless, compared to similar topologies, the converter has the highest duty ratio regulation limit, offering wider output voltage range.
To theoretically analyse the circuit operation, the following assumptions should be made: The converter operates in steadystate and in continuous conduction mode (CCM), the inductor values L 1 and L 2 are equal (L 1 = L 2 = L), all capacitors (C 1 , C 2 , C 3 , C 4 , C a and C b ) are considered large enough so that their voltage values remain approximately constant within a switching period and, finally, all active and passive devices are considered ideal (zero conduction and switching losses, zero voltage drop). The different conduction states within a switching cycle are shown in Figure 2.
In State I [t 0 , t 1 ], as shown in Figure 2(a), the group of Q 1a , Q 1b and Q 1c is switched-on, creating three separate and parallel current loops which charge the inductor L 2 , whereas the current of inductor L 1 is freewheeling through diode D 1 . For the first current path, stored energy in capacitor C 1 , as well as energy from the input, is transferred to L 2 inductor through States II and IV, (c) State III C 3 and C b , while charging them. The path is closed back to C 1 through the load and D 1 and back to V in through the load, D 1 and C 2 , while charging it. Within the second current loop, C 4 is discharging, transferring its energy to L 2 , while charging C b . The second path is closed back to C 4 through the load and Q 1b . Finally, since Q 1c is turned-on, a third current path is created, and energy from C a is transferred to L 2 through Q 1c and C b , while charging C b . The third loop is closed back to C a through the load and D 1 .
In State II [t 1 , t 2 ], all six transistors are switched-off. During this state, both inductors are discharging through their corresponding diodes, transferring the energy stored in them from the previous charging states to the load. In addition, the input capacitors C 1 and C 2 are charging from the input, correcting any deviation from their nominal voltage value. The circuit operation during this state is shown in Figure 2 In State III [t 2 , t 3 ], the operation is symmetrical to State I as the second group of transistors (Q 2a , Q 2b and Q 2c ) is switchedon, charging the inductor L 1 while L 2 current is freewheeling through D 2 . As shown in Figure 2(c), the inductor L 1 is charg-ing through three different current paths. Within the first current loop, the capacitor C 2 is connected in parallel with the input source and C 1 , transferring their energy to L 1 . The current loop is closed back to C 2 and V in through the load, D 2 , C b by discharging it, C 4 by charging it and Q 2a . Regarding the second path, C 3 stored energy is transferred to L 1 , through Q 2b and C a , while charging C a . The second loop is closed back to C 3 through the load, D 2 and C b , while discharging it. Finally, for the third current path, C b is discharging, transferring a portion of its energy to inductor L 1 , through Q 2c . The third path is closed back to C b through the load and D 2 once again.
In State IV [t 3 , t 4 ], all transistors are switched-off, leading the inductor currents to freewheel through their corresponding diodes. State IV circuit operation is the same as in State II and can be described by Figure 2 The key waveforms of the proposed converter are presented in Figure 3. The voltage stress on each transistor depends on the capacitors voltage and, as will be proven later, the maximum theoretical voltage stress is always equal to V in /3, except for the transistor Q 1b , which is even lower (down to V in /6). This will allow the selection of transistors with low breakdown voltage values, which may have improved characteristics such as low R DSon , minimizing the conduction losses of the converter, which, as will be proven later, are not dominant to the total converter losses. The most important feature, however, is that during switch-on/switch-off transitions, the voltage across the transistors is lower than V in /3 and, in case of equal duty ratios, equals to V in /6, leading to reduced switching losses. On the other hand, the voltage across diodes D 1 and D 2 is lower than V in /3, and for equal duty ratios is V in /6, allowing the selection of diodes with low breakdown voltage, such as Schottky which offer low forward voltage and zero reverse recovery losses, and improving the converter efficiency even further.

STEADY STATE ANALYSIS
The dc voltage gain and the automatic current sharing of the proposed converter will be investigated only in CCM. Besides, for the same output power in discontinuous conduction mode (DCM), the peak and rms currents through the semiconductor devices would become extremely high, making the employment of the converter for high output current and high efficiency applications impractical.

DC voltage gain
During State I [t 0 , t 1 ], the inductor L 2 is charged by three different current paths. Hence, the voltage across L 2 for each loop should be equal to: Combining Equations (2) and (3), we conclude that C 4 and C a voltage values are equal: since V C4 = V Ca , Equations (2) and (3) are identical. Hence, by combination of Equations (1), (2) and (4), the C 1 capacitor voltage is: On the other hand, during State III [t 2 , t 3 ], the inductor L 1 is charged by three different current loops. Once again, the voltage across the inductor L 1 must be equal to: The combination of Equations (6) and (8), as well as Equations (7) and (8), leads to Equations (9) and (10) respectively: Hence, combining Equations (4), (9) and (10), it is derived that the capacitors C 2 , C 3 , C 4 and C a have always the same voltage value: Also, combining Equations (5) and (11), the C 1 capacitor voltage value is always equal to: Considering that the input voltage equals to the sum of the input capacitors C 1 and C 2 voltage: from Equations (11), (12) and (13), and after some manipulations, the voltage values of capacitors C 1 , C 2 , C 3 , C 4 and C a are always given by Equations (14) and (15), regardless of their capacitance or the converter duty ratio: On the other hand, the C b voltage value depends on the duty ratio of each state. In steady-state operation, V Cb can be calculated considering that the average voltage value of each inductor within a switching cycle equals to zero. Hence, for the inductor L 2 : where D a = t on,Q1group /T s is the duty ratio of Q 1 group of transistors (Q 1a , Q 1b and Q 1c ) and T s is the switching period. Likewise, for the inductor L 1 we have: (17) where D b = t on,Q2group /T s is the duty ratio of Q 2 group of transistors (Q 2a , Q 2b and Q 2c ). The combination of Equations (16) and (17), reveals that V Cb depends on both duty ratio values and equals to: The step-down voltage conversion ratio arises by substituting Equations (17) to (18), and after a few manipulations: From Equation (19), it is obvious that the dc voltage gain depends on the relation between D a and D b . In the case of equal duty ratios, i.e. D a = D b = D, the step-down voltage conversion ratio is six times higher than the IBC and is given by: Also, for equal duty ratios, V Cb is calculated equal to: which confirms the theoretical waveforms presented in Figure 3.

Automatic current sharing
One of the major features of the proposed topology is the automatic uniform current sharing between the two output inductors. The balance between the average inductor currents I L1 and I L2 , can be derived by analysing the charge balance of each capacitor within a switching cycle. For instance, in State I, the capacitor C b is charged by the inductor L 2 current, since they are connected in series. The charge change of C b is obtained by: where f s is the switching frequency. In contrast, during State III, C b is discharging by I L1 current, transferring its stored energy to the inductor L 1 . The change in C b charge equals to: Since the sum of the average inductor currents I L1 and I L2 is equal to the output current I o : (24) and due to the fact that Equations (22) and (23) must be equal within a switching period, it is proven that the average output current is automatically distributed to each inductor according to the following relations: Thus, in the case of equal duty ratios (D a = D b = D), the output current is uniformly distributed between the two inductors:

KEY DESIGN PARAMETERS GUIDANCE
As mentioned in the steady-state analysis, the converter operates in CCM and the capacitor voltage values are considered approximately constant. In practice however, a voltage ripple will appear on them due to the charging/discharging process within a switching period. What is more, not only the device voltage stress but the transistor and diode current stress should be quantified as well, to better understand their impact on the converter design. Therefore, to properly design the converter, these important features must be determined.

Minimum inductance value and inductor current ripple
As shown in Figure 3, in the private case of equal duty ratios, the inductor currents have the same average value as well as the same waveform, only shifted 180 • to each other. Hence, the current equation for each inductor within a switching period is given by: where the first two terms of the upper equation are the minimum inductor current I Lmin and the first two of the second one equal to the maximum current I Lmax . Combining Equations (20) and (28), the current ripple of each inductor with respect to the input voltage is: Regarding the minimum inductance value, the converter inductors operate in CCM when their minimum current I L1,2min is equal or greater than zero. Therefore, the minimum inductance can be calculated combining Equations (20) and (28), and should satisfy the following inequality: where I o,min is the minimum mean output current value in which the converter operates in CCM for a given value of ripple.

Transistor voltage and current stress
As mentioned earlier, the maximum theoretical voltage stress on every transistor is equal to one third of the input voltage (V in /3) except for Q 1b where is one sixth (V in /6), as shown in Figure 3. Regarding the transistor current stress, since in States I and III three parallel loops are created charging each inductor, the current flowing through every transistor equals to one third of the inductor current within DT s . Thus, using Equation (28) and after some mathematical manipulations, the RMS current value on each transistor can be quantified as:

Diode voltage and current stress
As shown in Figure 3, the diode voltage stress depends on the C b voltage. In the private case of equal duty ratios, the maximum diode stress is equal to one sixth of the input voltage (V in /6), allowing the selection of diodes with improved forward voltage and very low reverse recovery losses. In contrast, in this family of converters, the current stress is always high on the output diodes due to the low duty cycle values as well as the inherent nature of the converter where, during D a T s and D b T s intervals, the current paths charging the complementary inductor are closed through them. However, as shown in Figure 3, the diodes are not equally stressed. Although during D b T s all three current loops are closed through D 2 , during D a T s only two current loops are closed through D 1 . Therefore, the average current value for each diode (I D1 and I D2 ) is slightly different and can be calculated from Equation (28) equal to:

Capacitor voltage ripple
During the preceded ideal steady-state analysis, the capacitors were considered as ideal dc voltage sources with their voltage values unchanged within a switching cycle. However, when the transistors are switched-on, the current flowing through them creates a voltage ripple.
In the private case of equal duty ratios, the C b capacitor is charging and discharging in State I and III respectively, with the whole inductor current, since it is connected in series with both inductors during their charging state. Thus, the voltage ripple on C b after the end of each state can be obtained by: On the other hand, the capacitors C 3 , C 4 and C a are charging and discharging with a third of the inductor current each time. Hence, the voltage ripple on them after the end of each state is: The input capacitors C 1 and C 2 , are charging and discharging with i L1,2 /6, since the voltage source of the first current path of States I and III consists of two parallel voltage sources, supplying half of the i L1,2 /3 current each. Therefore, the voltage ripple on them after D a T s or D b T s intervals, is obtained by: Finally, the voltage ripple on the output capacitor C o is generated using the ac component of the output current only, before the capacitor. Since the output current equals to the sum of inductor currents, shifted by 180 • , the output capacitor current ripple can be calculated from Equation (28), after some manipulations: The voltage ripple on C o can be calculated using the conventional relation [50]: where f out = 2f s , since the i L1 +i L2 ac component has twice the switching frequency, due to the interleaved nature of the converter. By combining of Equations (37) and (38), C o voltage ripple is equal to:

TOPOLOGY HIGHLIGHTS AND COMPARISON
One of the greatest merits of the proposed converter is the flexible step-down voltage conversion ratio, which completely depends on the relation between the duty ratios of each converter phase. Especially in the case of equal duty ratios (D a = D b = D), the converter has a very high step-down voltage conversion ratio (D/6) which along with the extended duty cycle upper regulation limit (0.5), offers a very low but wide output voltage range. Also, the maximum voltage stress on the transistors is significantly lower than the input voltage, i.e. V in /3, regardless of the duty ratios relation, allowing the selection of devices with lower breakdown voltage, which might have lower R DSon . On the other hand, during switch-on/switch-off transitions, the voltage across transistors and diodes depends on the relation between D a and D b , but it is lower than V in /3 and in case of equal duty ratios, it is six times lower than V in , reducing the overall converter switching losses, as well as conduction losses due to the selection of low breakdown voltage diodes with low forward voltage. An additional merit of this converter is the inherent automatic current sharing to its interleaved phases without any additional circuitry or complex control methods since it only depends on the D a and D b relation. In the special case of equal duty ratios operation, the output current is uniformly distributed to the two inductors, offering very low output current ripple and, consequently, lower output voltage ripple, as well as simplifying the implementation process with the symmetrical design of the converter.
A comparison of the proposed converter with expanded versions of other recent topologies of the same voltage conversion ratio is presented in Table 1. The proposed converter has the same switch voltage stress as the other similar topologies, except for the coupled inductor converters, where the maximum voltage stress is, generally, higher for all transistors. More specifically, the transistor voltage stress in converter [41] is V in /2 but it employs ZVS during switch-on transitions, which allows for high efficiency due to low switching losses, despite the high voltage switch stress. The maximum switch voltage stress of the converters presented in [43] and [44], is also V in /2, and in some transistors depends on the coupled inductor turns ratio n. In the case of the same voltage conversion ratio (n = 0.5), the maximum voltage stress on these transistors is V in /3. During switching transitions, however, the switch voltage stress is V in /4 for these converters, leading to higher switching losses per transistor. Also, the diode voltage stress depends on the turns ratio n, where in the case of same voltage conversion ratio, the diodes are stressed equally to the proposed converter (V in /6). Comparing the number of semiconductor components, the number of transistors is the same as in [31,32,[35][36][37]41] and the number of diodes is lower than the other topologies and same to the converter in [44]. Converter [41] does not have any diodes, as the MOSFETs are operating synchronously, substituting the freewheeling diodes. One of the highlights of the converter under investigation is the lowest number of magnetic components, since it only employs two output inductors, reducing the overall cost of the topology. In comparison with [41] and [44], the converter employs more capacitors, but it lacks customized magnetic components with difficult winding process such as coupled inductors/transformers, counterbalancing the overall cost. What is more, the ZVS condition of converter [41] is difficult to achieve at a wide operating range, as it depends on the load current and needs substantial leakage inductance values. High leakage inductance values, however, affects the voltage step-down conversion ratio and increases the converter losses since higher amounts of leakage energy need to be recycled. In terms of control and design complexity, the converter can easily be driven by two phase-shifted pulses, reducing the need of a high amount of independent PWM generators, and thus, a costly microcontroller. Concerning the control algorithm challenges of this converter family, the authors in [25] present the optimal steady-state and transient mode control of the series capacitor buck converter. Finally, since the converter features the highest permitted duty ratio, it can operate in a wider output voltage range, making it suitable for a wide range of applications.
The efficiency performance of the proposed converter compared to other topologies is evaluated using PSpice and is, also, presented in Table 1. The same Si power MOSFET model with low breakdown voltage (IXFH70N30Q3 from IXYS, V DSbreakdown = 300 V) was selected for all converters and the same diode model RB238NS150 (V Rmax = 150 V) from ROHM semiconductor was used for every converter diode. To quantify the inductor copper losses, we assumed 0.2 mΩ/uH, mostly based on measurements conducted in the experimental set-up inductors (L 1 , L 2 = 70 uH). Also, a typical ESR value of 1.6 mΩ was used for every converter capacitance, selected according to the capacitor models used in the experimental prototype, which are shown later. Finally, it is worth mentioning that since the converters operate in CCM, the core losses are a small portion of the converter losses and are, therefore, neglected. The components used to simulate the converters in PSpice are summarized in Table 2.
The efficiency of each topology is calculated for two operating points: (a) P o = 250 W, V in = 500 V, V o = 12 V and (b) P o = 250 W, V in = 500 V, V o = 24 V. As it is shown in Table 1, the proposed converter has higher efficiency compared to the coupled inductor converters [41,43,44], mostly due to the lower voltage stress on the transistors. On the other hand, compared to the topologies with higher number of output buck stages (inductor-diode) [31,32,[35][36][37], it has slightly lower efficiency, since the RMS current values on the inductors and diodes are higher. It is worth noticing that the converters [31] and [44] cannot operate at V o = 24 V due to duty cycle limitations.   Two with: V in ∕2 and two with: Transistor voltage stress during on/off transitions Efficiency:  In general, the greater the number of components is, the higher the converter efficiency is, which is illustrated in Figure 4. According to this figure, the proposed converter efficiency stands at the middle: just below of the converters with a higher number of components but significantly above of the converters with, generally, a lower number of semiconductor devices. Hence, the converter selection for each application depends on several factors such as the number of components, the duty ratio range etc., and not only the efficiency.

EXPERIMENTAL ANALYSIS
To validate the operation of the proposed converter, a 250 W, wide voltage input-wide voltage output range laboratory prototype operating in 100 kHz switching frequency was implemented and is shown in Figure 5. The appropriate PWM pulses to drive the MOSFETs were generated by a TMS320F28377S Development Board by Texas Instruments (TI).

Converter parameters and practical component selection
The components used to build the prototype and the overall converter parameters are presented in Table 3. The com-    Regarding the transistor selection, the STW36N55M5 MOS-FETs from STMicroelectronics were selected, which offer low R DSon , combined with low parasitic capacitors (C oss , C rss ) and, consequently, low current rise (t ri ) and fall (t fi ) times. This will allow the reduction of conduction and switching losses, improving the overall converter efficiency. The cost criterion also contributed to the final transistor selection.
Since the switches of the proposed converter are floating, the driving circuitry can be implemented in two ways: either by six (6) independent gate driver circuits with separate isolated power supplies, or by using the bootstrap driving technique in three (3) transistor pairs which are in half-bridge configuration and are switching in complementary fashion: Q 1a -Q 2b , Q 1b -Q 2a and Q 1c -Q 2c , considerably reducing the isolated power supplies to only three (3). In our case, the first way was preferred and the MOS-FET gate drivers ISO5451 by TI were selected, which offer isolation between the PWM microcontroller signals and the power circuit and can directly drive the MOSFETs of the prototype without any additional isolation or amplification stage. They, also, feature negative gate voltage during switch-off and active Miller clamp to avoid undesirable phenomena such as the self turn-on phenomenon, which is a common problem in converters with fast switching operation and floating switches, such as inverters, multilevel inverters etc. [51], [52]. In addition, six isolated dc/dc converters MEV1S1215SC by Murata were used as power supply of the high-side/output stage of the MOSFET drivers.
As proven in Section 4, the diodes are stressed with high current values, calculated from Equations (32) and (33), under the worst case scenario, which is the V in = 400 V, V o = 12 V and P o = 250 W case, where the output current reaches its highest values, resulting to significant conduction losses. Thus, the diodes selected for this application are Schottky, which have low forward voltage and almost zero reverse recovery losses, reducing the transistors current stress due to the reverse recovery current and improving the converter efficiency. The circuit capacitors were selected with the following criteria: low voltage ripple, low equivalent series resistance (ESR), high current capability and cost. The capacitance values are initially estimated using the relations Equations (34)-(36) and according to the specifications presented in Table 3 regarding the maximum voltage ripple, which is selected to be lower than 2.5% of the nominal value under the worst-case scenario. In our case, the maximum voltage ripple on the capacitors appears at V in = 300 V, V o = 18 V and P o = 250 W. Since currents of high values and frequency flow through the capacitors, MKP capacitors were selected which have very low ESR in a wide frequency range compared to electrolytic capacitors. What is more, to increase each capacitor current capability and reduce ESR even further, each circuit capacitor component consists of several parallel connected capacitors. The final capacitor choice, however, was made with the cost crite- rion, since they were less expensive than other choices which satisfied the above requirements, despite their high breakdown voltage.
Finally, the inductors were calculated according to the specifications presented in Table 3: The maximum current ripple appearing on the inductors should be ≈20% of the output load current in the worst-case. For the inductors, the maximum current ripple appears at V in = 400 V, V o = 24 V and P o = 250 W.

Steady-state, start-up and transient state waveforms
The key steady-state waveforms which validate the converter operation are presented in Figures 6-10. The converter operates close to its nominal operating point for equal duty ratios (D a = D b ≈ 0.18), i.e. P o ≈ 225 W, V in = 400 V and V o = 12 V. As shown in Figure 6, the inductor L 2 is charging when the transistor Q 1a is switched-on. Also, the L 1 and L 2 currents are in 180 • phase to each other and their average current values are almost equal. Slight deviations to the current ripple might exist because of the inductance tolerance between L 1 and L 2 . In Figure 7, the Q 1group voltage along with D 2 voltage waveforms are presented. It is confirmed that the maximum voltage stress on the transistors during steady-state operation equals to V in /3 ≈ 133.3 V except for Q 1b transistor where is V in /6 ≈ 66.7 V. Also, the stress on the transistors during switch-on/switch-off   Figure 8, have the same voltage stress values as Q 1group and D 2 respectively. The small voltage ringing appearing on the experimental waveforms is due to the circuit parasitic inductances as well as the very fast switching transitions of the power devices. This must be considered during the converter design process with the selection of devices with higher breakdown voltage. Also, the capacitor voltage levels for all converter capacitors are presented in Figures 9 and 10. In Figure 9, V C1 , V C2 and V Cb are approximately equal to the theoretical values calculated from Equations (14), (15) and (18) respectively. The other three capacitor voltage levels V C3 , V C4 and V Ca are shown in Figure 10, and are equal to the theoretical ones calculated from Equation (15).
A demonstration of the most significant converter voltage and current values for this operating point is presented in Table 4. The comparison between the theoretical and the measured experimental values validates the theoretical analysis of the converter. Some slight deviations from the theoretical values are due to several factors such as the capacitance tolerance, higher practical duty cycle value than the theoretical due to losses etc.
The most significant capacitor voltage levels during startup are illustrated in Figure 11. Initially, the input voltage is equally shared between the two input capacitors (V C1 = V C2 = V in /2 = 200 V) and the series capacitor C b is not yet charged. After the PWM sequence begins, the capacitors will reach their steady-state values without any additional control method or additional circuitry. However, it should be noted that since the input voltage is shared initially between the input capacitors while the other circuit capacitors are not yet charged, the transistors Q 1a and Q 2a will be stressed with V in /2. Thus, the "practical" voltage stress on the transistors during start-up

FIGURE 12
Overall system with PI controller process is V in /2 and they should be selected for such breakdown voltage.
Regarding the control, the conventional PI control scheme was selected to regulate the output voltage, which is presented in Figure 12. The only limitation is the differential sensing of the converter output voltage due to the non-common ground feature of the converter. The transient response of the proposed converter for a step change of the input voltage is presented in Figure 13. The initial converter operating point is at V in = 400

Efficiency and power loss distribution
Efficiency measurements for different input and output voltages, as well as a wider frequency range, were carried out using the precision power analyser LMG500 of ZES Zimmer manufacturer. The converter efficiency was measured in three different cases: wide output voltage range, unregulated input voltage and variable frequency. The converter efficiency in the case of wide output voltage range is presented in Figure 14. The input voltage was set to 400 V and the maximum output power goal was set to 250 W. As expected, the efficiency is higher for higher output voltages, reaching 94% in the case of V o = 24 V, due to the lower current stress on the output diodes, as well as because of the lower copper losses on the inductors, since in the case of V o = 12 V, the average diode currents and the RMS current inductor currents are reaching values higher than 10.5 A. For comparison reasons, the efficiency curve for the worst case of operation, i.e. V in = 500 V/V o = 12 V is presented as well. Even though the efficiency is the lowest one, it is still higher than 81% at the low power range and up to 87% for the nominal load. More specific, comparing the efficiency with the V in = 400 V/V o = 12 V case, it is just 3% lower for small load values and only 1% for the full load operating point.
In the second case, presented in Figure 15, the output voltage was set to 18 V and the parameter was the input voltage. As it is depicted, for high power range the distance between the curves is almost negligible. On the other hand, in the low power range, the efficiency is up to 1% higher for lower input voltages, which signifies that the switching losses due to the higher input voltage are more dominant within this area. The third case is presented in Figure 16. In this case, the efficiency was measured for three different switching frequencies: 100 and 150 kHz with the same inductors L = 70 uH and for 50 kHz with twice the initial inductors (L = 140 uH). On the one hand, the increase in frequency without changing the inductors showed that the switching losses have linear effect to the converter efficiency, as the two curves are almost parallel to each other for the whole output power range. In contrast, the experiment at 50 kHz with L = 140 uH, indicated that in low power range, the converter performs better with lower frequency and bigger inductors whereas in higher power range, higher frequency is preferred, leading to smaller inductance values, and consequently, lower copper losses. Hence, for high output current applications, the selection of a higher switching frequency might be of great merit for the converter efficiency.
The converter power loss distribution in the case of V in = 400 V, V o = 18 V and f s = 100 kHz is presented in Figure 17. Each type of losses is calculated from the converter losses equations (shown in the Appendix) and expressed as a percentage of the total converter losses for each output operating point. The voltage and current values, as well as other converter parameters used to calculate the losses are presented in Table 5. The calculations were made in MATLAB, where parameters like voltage fall (t fu ) and rise (t ru ) times were calculated using the capacitance variation diagram in STW36N55M5 datasheet, the driver voltage value, the external gate resistance etc. Other parameters like t ri and t fi were slightly readjusted and  R DSon was selected at 40 • C. The diodes forward voltage and resistance were selected at the same temperature as well.
As expected, the diode conduction losses are the most dominant losses within the whole output power range, due to the high current stress of the output diodes. As Schottky diodes were used, the reverse recovery losses are not taken into account. The transistor switching losses have a significant impact on the converter losses, especially in the low and middle power range, which shows that transistors with low switching times are preferred for this application. The transistor conduction losses percentage is increasing as the output power increases but still, it remains low, due to the low current stress on the transistors as well as the low R DSon , such as in our case. Also, as the output power increases, the inductor copper losses become more dominant in the efficiency degradation. Finally, "other losses" represents a sum of all capacitor conduction losses due to their ESR, as well as the magnetic core losses. Within the low power-range, "other losses" are significant mostly due to the magnetic core losses, which however, remain almost constant for the whole power, as it can be seen from Equation (50). On the other hand, as output power increases, these losses are relatively small, due to the selection of capacitors with very low ESR values.

CONCLUSION
This work is focused on a new high step-down voltage conversion ratio topology. The converter offers a very high stepdown ratio, which in the case of equal duty ratios is six times higher than the conventional buck (D/6) and along with the extended duty cycle regulation limit (D max = 0.5), which is the highest compared to topologies of the same family and conversion ratio, it offers a wide output voltage range. Despite the use of six transistors, the converter can be driven by only two PWM pulses with 180 • phase-shift offering simplicity to the overall control. Another major feature adding to simplicity, is the automatic current sharing between the two interleaved phases, which in case of equal duty ratios is also uniform. In terms of cost, the converter has the lowest number of magnetic components and the second lowest number of semiconductor components compared to familiar topologies of the same voltage conversion ratio. By employing the switched/series capacitor concept along with the appropriate component interconnection, the voltage stress on the semiconductor devices during switching transitions is reduced, improving the overall converter efficiency by lowering the switching losses. As shown in the experimental analysis, the converter demonstrates exceptional efficiency for a wide input/wide output range of applications, making a perfect fit for high efficiency applications.

APPENDIX A
The loss equations of each component of the proposed converter are extracted according to the theoretical waveforms presented in Figure 3 and the design guidance equations presented in Section IV. The switching losses calculation was conducted according to the application note [53], which also considers the parasitic capacitors of the transistors, as well as the driver voltage and the transistor gate resistance values. The inductor copper losses are mainly due to the dc resistance, since the inductor current ripple is relatively minor compared to the average current, as well as the use of Litz wire to neglect the skin effect. The core losses are calculated using the iGSE [54] and are proven to be of minor significance for high output power values. Hence, the losses of each component are given from the following equations: 1. Conduction losses per transistor: 2. Switching losses per transistor: P sw,Q = P ON ,sw,Q + P OFF ,sw,Q ⇒ P sw,Q where t ri and t fi are the current rise and fall times given from the device datasheet, and t fu and t ru are the voltage fall and rise times, calculated according to [53]. (

Conduction losses of
where V F1 and V F2 are the forward voltages, and R D1 and R D2 are the resistances of D 1 and D 2 diodes, respectively.
1. Reverse recovery losses per diode: t rr I RM f s (44) where s is the diode softness factor, t rr is the recovery time and I RM is the peak reverse current. These three parameters can be determined from the component datasheet, depending on the application specifications. In our case, these losses are neglected due to the use of Schottky diodes.