An improved asymmetrical multi-level inverter topology with boosted output voltage and reduced components count

This paper presents an improved Multi-level Inverter topology utilizing the concept of boosting-capacitor and two DC sources with reduced switches count for generating 17-level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H-Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce ‘n’ level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are veriﬁed. Nearest level control is used as the modulation technique.


INTRODUCTION
In recent years, the use of renewable energy resources has shifted the attention of researching community towards fast and effective power conversion techniques due to the growing concern over the environment. Multi-level inverters (MLI) have emerged as an effective, practical and feasible option for improved and high-power quality power conversion [1]. They produce stepped output voltage waveform through several DC source(s), switching them in a particular manner with power conductor switches [2,3]. The stepped voltage waveform has several advantages like reduced switching stress, increased waveform quality in terms of reduced total harmonic distortion (THD), better electromagnetic consistency, lower switching and conduction losses and improved efficiency [4,5]. Owing to these advantages, MLI has found application in several sectors such as micro-grid [6], distributed generation [7,8], power systems [9,10] in high voltage direct current (HVDC) applications [11]. Some of the earliest work on multi-level inverters is covered by Lai and Peng in [12]. The earliest work for asymmetrical inverters can be traced back to Manjrekar et al. [13,14]. In their work, the authors proposed a new binary method of choosing the magnitude of DC sources for Cascaded H-Bridge topology. The number of output levels showed a dramatic rise with the same number of components as compared to the symmetrical counterpart. The author is [15] proposed a novel topology to produce stepped output; it employed a principal DC source bus and the rest of the DC buses were capacitor banks. The converter control algorithm stabilized the voltage across capacitors. This topology offered a reduction in devices, but it required a complex algorithm for voltage balancing. In [16], the author proposed another novel topology that employed a single DC source and three capacitors to produce seven-level output. The topology is suitable for solar PV-grid applications. Although the topology offers an advantage in requiring only a single DC source, it suffers from a higher total component count. Babaei et al. [17] proposed another capacitor-based asymmetrical topology. The topology offered better performance in THD and employed lesser components and increased the output level considerable. Still, it suffered from the voltage balancing issue for the capacitors. The topology required special attention for capacitor balancing, thus increasing the complexity of the control algorithm.
Gautam et al. [18] proposed another hybrid topology which employed two DC sources with capacitors. The number of capacitors depends on the output level required. The topology offered fundamental switching, equal power sharing among the cells, but it required the switches of different power ratings; also, the capacitors balancing of voltage needed, making the control algorithm complex. Jain and Sonti [19] presented another topology specifically for solar PV-based applications. The topology utilized an equal number of DC sources and capacitors. The topology offered reduced conduction losses as the number of switches in conduction path are reduced and lower commonmode current making it highly suitable for solar PV applications [20]. Apart from these, many different works are proposed in the literature for asymmetric and symmetric topologies employing capacitor banks [21,22]. This paper has exploited the switch capacitor circuit's boosting capability and the flexible nature of H-Bridge inverter. In the proposed topology, two DC sources and three capacitors so placed between two Half-Bridge to maintain the modularity of H-Bridge and reduce the switching stress on each Half-Bridge switch. The proposed topology has added advantage that it produces inherent negative levels, thus reducing the switching stress and the device count and cost.
The basic cell of the proposed asymmetric topology produces 17-level output in an asymmetric configuration; nevertheless, the basic cells can be cascaded to produce n-level output, thus retaining the modularity. The basic cell employs two DC sources and is utilized in 2:3 ratio of magnitudes. The topology can be used in symmetric manner, also where both the DC sources are of equal magnitude. In that case, the topology offers 13-level output. The novelty of the work lies in the fact that the topology combines the advantages of H-Bridge with those of boosting voltage by incorporating a switched capacitor circuit. The topology is very much suitable for grid-tied applications and solar PV system applications as it has reduced components counts and can be easily extended to the threephase structure. The novelty of the work and the critical points of the proposed topology can be summarized in the following points: (a) The proposed topology offers voltage boosting with 1.6V in gain in the asymmetric configuration. (b) The capacitors are self-balanced because of the utilization of the redundant states in switching. (c) The capacitor size is small, thus making it feasible. (d) The topology offers 17-level output thus reducing the THD in the output. The output can be directly fed to the grid as the IEEE standard is met to cut the cost of the filter, making it even more feasible. The proposed topology is suitable for interfacing different renewable energy sources with the utility grid due to its advantages like lower harmonics, lower components and economically feasible operation. The output from various renewable sources is predominantly DC. For the solar PV, the output supplied by the MPPT serves as the DC link. A DC-DC converter can be used to form the appropriate DC link of required magnitude. These DC links are fed as input to the proposed inverter and converted into AC with low harmonics. The output of the multilevel inverter can be controlled through the current controller. This is done in order to control the active and reactive power flow.
The paper is organized as follows: Section 2 discusses the topology and its working; the switching table is explained, and all the necessary calculations are performed. Section 3 deals with the generalization of the basic cell through cascading. All the necessary equations are formed. In Section 4, the simulation results of the basic cell are shown and discussed. Section 5 deals with the experimental validation of the proposed topology. Section 6 discusses the results and compares the topology in terms of components used with other topologies, and finally, the paper is concluded in Section 7.

TOPOLOGY DESCRIPTION
The proposed topology is depicted in Figure 1. The magnitudes of the two DC sources can be symmetric and asymmetric in magnitude. In asymmetric combination, DC sources are in 2:3 ratio producing 17-level output voltage. Ten unidirectional switches are employed along with a single bidirectional switch. The unidirectional switch means two-quadrant operation while the bidirectional switch is a four-quadrant switch. Both the insulated gate bipolar transistors (IGBTs) of the bidirectional switch can be fed through a single gate driver circuit. The topology makes the use of boosting voltage capacity of switched capacitor topology. It is possible because of the isolated nature of the capacitor C 1 . The modified switching strategy keeps the capacitor C 1 charged to 3V d voltage level. Through proper switching, this can be exploited to boost the voltage by operating 3V d DC source in series with the C 1 . Where V d is equals to one step of the voltage in the output staircase waveform. The DC voltage source V 2 is required to control the charging of C 2 and C 2 '. Although it is possible to charge the C 2 and C 2 ' through the V 1 utilizing the redundant state switching strategy, that approach will reduce the output levels. Hence, to make the C 2 and C 2 ' independent of V 1 , the second DC Source V 2 is used, which will increase the output levels. Thus, the topology is a hybrid amalgamation of H-Bridge and switched capacitor, retaining all the positive characteristics of both configurations. The modularity of H-Bridge and the boosting of the voltage level of switched capacitor, are incorporated in this topology. In the following section, operation of the basic circuit producing 17-level output is discussed in detail. Table 1 shows the switching configuration for the various output voltage level. Current flow path and modes of operation during one complete cycle is shown in Figure 2. The zero levels can be produced in two states, giving the redundant states, which helps in capacitor voltage balancing. The first positive voltage is generated by turning on switches S 2 , S 10 , S 8 and S 5 . This combination brings the capacitor C 2 ' into the conduction path and delivers the V d level at the output. During this period, S 3 and S 6 switches are also turned on to charge the capacitor C 1 to 3V d .
Similarly, 2V d are generated by bringing both the capacitors C 2 and C 2 ' into the conduction path. This is done by turning on S 2 , S 9 , S 8 and S 5 . Again, S 3 and S 6 are turned on to exploit the circuit's redundancy and charge the capacitor C 1 . 3V d can be generated in two ways, either by bringing the 3V d DC source into the conduction path or by bringing the capacitor C 1 which is charged to 3V d into the circuit, thus providing further redundant states. To keep the voltage balanced across capacitor C 1 , the 3V d DC source is utilized to produce the output level by turning on the switches S 1 , S 11 , S 8 and S 5 . Also, S 3 and S 6 are also turned on to keep the capacitor C 1 charged. To produce the 4V d , the capacitor C 1 or the DC source with 3V d magnitude can be utilized. The DC source with 3V d magnitude is again preferred, and the capacitor C 1 is kept charged while bringing the 3V d DC source and the capacitor C 2 ' into the conduction path. For 5V d output level, the 3V d DC source, as well as both the capacitors (C 2 & C 2 '), is brought into the conduction path by turning on S 1 , S 9 , S 8 and S 5 . For 6V d output level, both the 3V d DC source and the capacitor C 1 are turned by switching the S 1 , S 11 , S 4 and S 8 . For 7V d output level, an additional capacitor C 2 ' is also brought into the conduction path in addition to the previous combination. Finally, for 8V d , all the three capacitors and the 3V d DC source are brought into conduction path by turning on S 1 , S 9 , S 4 and S 8 .
During the negative cycle, there is no redundant path for the capacitor charging. For -V d , switches S 1 , S 10 , S 3 and S 7 are turned on, bringing the C 2 into conduction path and the direction of current is reversed. For −2V d , both the capacitors C 2 and C 2 ' are brought into the reverse conduction path by turning on S 1 , S 11 , S 3 and S 7 . Capacitor C 1 produces −3V d across the load. Again for −4V d , capacitors C 1 and C 2 are brought into reverse conduction path in series by turning on S 2 , S 10 , S 6 , S 5 and S 7 . −5V d is produced by bringing all the three capacitors  into series. This is done by switch combination S 2 , S 11 , S 6 , S 5 and S 7 . For −6V d both the 3V d DC source and the capacitor C 1 are made to act in series in reverse conduction path. For −7V d , an additional capacitor C 2 is also brought in series with the previous combination. Finally, for −8V d , all the capacitors and 3V d source are put in series in reverse conduction path by turning on S 2 , S 11 , S 3 , S 4 , S 5 and S 7 . Table 1 shows the switching strategy as well as the capacitor C 1 charging and discharging states. Since the other two capacitors, i.e. C 2 and C 2 ' are continuously connected across the DC source, they are constantly in a charged state. However, capacitor C 1 is isolated and therefore, requires proper charge balancing attention. To maintain adequate charge balancing for C 1 , the author has modified the switching strategy to provide the redundant states for capacitor charging.

Capacitor sizing
The size of the capacitor plays a vital role in determining the feasibility of the converter. The size of the capacitor depends upon the energy handled by the capacitor in one complete cycle. Considering Table 1 of the switching and Figure 3 which shows the 17-level output and the switching strategy, it can be seen that for capacitor C 1 , the maximum discharging time is from θ 6 to π-θ 8 . Similarly, C 2 discharges for positive half cycle, i.e. (π−0) and C 2 ' acts complimentary to the C 2 because of their series connection and charge balance, thus C 2 ' discharges for the negative half cycle (2π-π). Since the capacitor C 1 involves most complex equations, the capacitor balancing process is shown for C 1 . For C 2 and C 2 ', the process remains the same. For the discharging period of capacitor C 1 , the change in charge is given by: where i L represents the load current. Based on the modulation index, both θ 6 and θ 8 can be calculated as follows: Further considering a purely resistive load of resistance R, the maximum charge ripple ΔQ 1 is calculated by the following equation: where f s is the switching frequency, and 8V d is the maximum voltage that appears across load R. Now for capacitor C 1 , the maximum voltage ripple can be calculated by Equation (5). The capacitor's optimum size is calculated by using (6). Using the same procedure, the capacitor size is calculated for C 2 and C 2 '.

Capacitor balancing
To analyse the two series capacitors' voltage balancing across the DC source, that part of the topology is explored separately and shown in Figure 4(a). The voltage balancing of capacitors depends upon the average power during the various intervals [23,24]. The typical current and voltage waveforms of this part is also shown in Figure 4(b) and it shows that the current waveforms in 0−π interval and then π−2π interval are the same. For the interval α 1 − α 2 , the waveform follows the same pattern as it follows in [(π+ α 1 ) − (π+ α 2 )]. The same is true for the rest of the intervals. This is because of equal capacitance (C 1 = C 2 ), both capacitors are initially charged to an equal voltage value, i.e. V 2 /2. The switching is designed in such a way that if for α 1 − α 2 , capacitor C 1 is utilized then for the interval [(π+ α 1 ) − (π+ α 2 )], C 2 will be utilized. This process is validated as for the positive half cycle, and the lower capacitor is made to come in the current path. In contrast, for the negative half cycle, the uppermost capacitor is made into the current path. Thus, in light of Figure 4 and the above discussion, the following equations hold truth: and For the above equations, it should be noted that v o and i o represent the voltage and current waveform corresponding to the cell shown in Figure 4(a) only and does not mean the output voltage and current of the converter. Thus, the average power during the various intervals remains same and maintaining the voltage across the capacitors. During the interval [(π−α 1 )−π], the current falls to zero as the capacitors are cut off from the current path. This describes the voltage balancing for the series capacitors with a DC source acting independently. This whole arrangement of DC source with series capacitors is utilized with a switched capacitor, this does not change the working of the series capacitors, only as the levels in voltage are increased because of the previously switched capacitor, Equations (7) and (8) still holds thus maintaining the voltage balance.

Inrush current control
In one complete cycle, the switched capacitor, C 1 is charged and discharges several times. The inrush charging current is mainly determined by the gap between the charging voltage and the initial capacitor voltage at the time of charging and on the circuit parameters of the charging loop. Figure 5 depicts the simplified charging loop. For the sake of reliability and protection, the maximum difference between the charging voltage, i.e. V 1 and the capacitor (C 1 ) voltage is seen. The maximum gap between these two will draw the maximum possible inrush current. This maximum gap occurs when the first charging begins, and the difference is 3V d . The following expression can approximate this gap: The approximate peak value of charging current then can be found as: where R cr = r cr is the total parasitic resistance of all the charging loop components V FD is the lumped forward drop of all the charging loop components. This maximum inrush charging current can be handled by inserting a small inductance L r in the charging loop. L r can be modelled based on maximum inrush charging current. It acts as a short circuit during the steady-state operation and protects against the maximum charging current during the transients. It reduces peak of inrush charging current and provides di/dt protection. To avoid any negative impact, this inductance value is kept reasonably small and set below 1 μH.

Total standing voltage (TSV) calculation
TSV is an important aspect while deciding the switch ratings. It refers to the maximum voltage the switch has to bear during its blocking state. From the circuit, it is clear that the switches S 1 , S 2 , S 6 , S 8 and S 10 Also, the diode D 1 has to withstand maximum stress of 3V d .
Total Standing Voltage (TSV) Sometimes, per-unit TSV, which is the ratio of TSV and the maximum output voltage, is also calculated. In this case, Per Unit TSV, TSV (pu) = TSV∕(Peak Output Voltage) The voltage stress distribution on various switches is shown in Figure 6.

CASCADED STRUCTURE
The basic structure of a cell produces 17-level output; however, the topology can be extended by cascading different cells to produce a higher number of levels. For generalization, a number of cells are cascaded together. The different characteristics associated with the cascaded structure are shown below in terms of equations. For 'k' cells cascaded together: Number of DC sources required, N DC = 2k, Number of capacitors required, N C = 3k Number of switches required, N sw = 11k (18) Apart from these equations, the relationship between N L , N DC and N sw can also be formulated as below: Figure 7 depicts the generalized structure of the topology utilizing different cells cascaded together.

RESULTS AND DISCUSSION
A basic cell of the topology proposed and discussed above produces 17 levels in asymmetric DC sources combination and 13 levels in symmetric mode. The converter is controlled using  Figure 8 shows the application of NLC switching technique. The switching table is depicted in Table 1. Simulation analysis and hardware validated of both the topologies has carried out and discussed in the following sections.

Simulation analysis
The basic cell is simulated in MATLAB/Simulink environment. The simulation is performed for constant and varying load conditions to check the static and dynamic performance of the proposed topology. The values used for C 1 and C 2 in the simulation are 2.2 mF each. For symmetric operating, the value of the DC sources are V 1 = V 2 = 150 V whereas for asymmetric operation, the DC sources are V 1 = 150 V and V 2 = 100 V. Figure 9(a) shows the output voltage and the current waveform for constant RL load for symmetrical configuration, thus producing 13-level output. Figure 9(b) depicts the output voltage and current waveforms for 17-level output. The load is specified to be 100 Ω + 80 mH in both cases. The harmonic analysis is also shown alongside. The THD in the output voltage is 4.85% for 17-level output with all the individual harmonics being less than 5%. For 13-level output, the output voltage offers 6.37% THD.

Experimental validation
The inverter prototype is prepared in the laboratory to confirm and validate the performance and operation of the topology. Table 2 specifies the various characteristics of the components used. The output waveform shows the stable voltage levels are produced. The current drawn by the load is also depicted to confirm the proper working of the topology. Figure 10 illustrates the output voltage and current waveform for symmetrical configuration, i.e. for 13-level output while Figure 11 deals with the asymmetrical configurations, i.e. 17-level output. Figure 10 depicts the experimental validation for the symmetrical operation of the proposed topology. It produces 13-level output which can be seen in the Figures 10(a) and (b) depicts the output voltage and current for R (150 Ω) and RL (150 Ω and 120 mH) load, respectively. The current waveform is slightly lagging due to the lagging power factor of the load in Figure 10(b). Figure 10(c) shows the dynamic operation by changing the load from infinite (no load), to 150 Ω and then to 75 Ω. It can be seen that the envelope of current waveform goes on increasing as the load is decreased while the voltage waveform remains unchanging. Figure 10(d) shows the effect of change of the power factor of the load. As the power factor is changed from the lagging to unity, the current waveform is changed accordingly. The transition is smooth without any oscillation or current spike. Figure 11 deals with the results obtained for asymmetrical operation of the topology, and it can be seen that the topology produces 17-level output. Figure 11(a) depicts the output voltage and current for RL load, while Figure 11(b) shows the change in the load power factor. Again, it can be noticed that the transition in the current waveform is without any disturbance. Thus, the operation of the topology in both modes is validated through the experimental setup.

POWER LOSS ANALYSIS
The power losses associated with the switches involved are important as the converter's efficiency depends upon the losses. There are mainly two types of losses associated with a switch, conduction loss and switching loss. Since a power, the electronic switch includes both transistor and diode, the conduction loss across both is calculated as follows [25][26][27]: where T and D in the subscript represent Transistor and Diode, respectively, V T and V D are the voltages drop across the Transistor and Diode during the conduction period, R T and R D represent the conduction resistance, i(t) is the current flowing through switch during the conduction period while β is a constant related to the Transistor specifications and can be noted down from the Datasheet. The total conduction losses of a switch are the sum of the two equations above. The average conduction loss of a converter depends upon the number of transistors and diodes conducting at an instant. Considering N T transistors and N D diodes are conducting at an instant t, then the average conduction loss will be The switching losses are calculated based on energy loss. These include turn-off losses and turn-on losses and can be calculated as described in [8]: Similarly, Where E off,k and E on,k are the energy loss during the turnoff and turn-on period of the switch k, t off and t on are the turnoff and turn-on time while t is the time period, I is the current through the switch just before turning off and I' is the current through the switch just after turning it on, V sw,k is the voltage of the switch after it is turned off. The power loss due to switching transitions in one complete cycle can be written as: where f is the fundamental frequency, N on,k and N off,k are the number of times kth switch turn-on or turn-off in one fundamental cycle. Finally, total losses are given as: To check the performance of the topology, power losses are calculated at three different loads which are specified as Z 1 = 50 Ω, Z 2 = 50 Ω + 40 mH and Z 3 = 100 Ω + 80 mH. Figures 12(a) and (b) depict the switching and conduction losses in the topology for both the three loads, respectively. Moreover, total power loss with the efficiency variation is also shown for all the three loads in Figure 12(c). Efficiency versus power output curve is depicted in Figure 12(d).

COMPARATIVE ANALYSIS AND DISCUSSION
The following section validates the proposed topology by comparing the other topologies present in the literature.

Number of levels versus number of IGBT
For the comparison purpose, N L /N IGBT ratio is included by the author. This ratio gives insight into the cost-effectiveness of the topology. Higher the N L /N IGBT ratio, fewer would IGBTs used, and higher would be the output levels. Thus, better quality output with a lower number of IGBTs and more feasible the topology is. Some of the topologies utilize bidirectional switches. The N IGBT and N gd are different as a bidirectional switch combines two IGBTs but fed by single gate driver. Based on the above table, it can be seen that the proposed topology has 1.42 N L /N IGBT ratio. Topologies present in [31] and [35] have higher N L /N IGBT ratios, but they utilize many DC sources and have no boosting capability. Topology in [32] has the lowest N L /N IGBT ratio while the proposed topology has second-best ratio among the topologies included above. Thus, based on the above discussion, it is clear that the proposed topology is feasible for renewable energy applications.

Number of levels versus number of DC sources
The number of DC sources play an important role in the application feasibility of the topology. Higher the number of DC sources, more would the cost and voltage stress on the switches. From Table 3, [33] has the lowest number of DC sources. It only utilizes a single DC source but produces nine-level output with no boosting capability and utilizing three capacitors. The proposed topology utilizes only two DC sources and gives 17level output; thus, it is clear that the proposed topology offers a feasible option for better power quality.

6.3
Number of levels versus TSV pu and MBV pu TSV (pu) is an important aspect while determining the feasibility of a topology as it is an indirect measurement of the rating of the IGBTs used. Higher the TSV pu , more would be the rating and cost of the IGBT. The proposed topology has 4.5 pu of TSV. The topology in [28] has the best TSV pu of 4 only, but it requires a higher number of DC sources. Among the 17-level topologies, the proposed topology offers relatively good TSV. Figure 13(a) shows the graphical comparison of TSVs. Another critical parameter is MBV pu . It is the representation of the average blocking capability required for a switch in the topology. Lower the value of MBV pu , better it is. From the above table and discussion, it can be seen that the proposed topology has the best MBV pu among all the work discussed. It signifies that on average a switch in proposed topology has to withstand the stress of only 0.675 pu. Thus, from the above discussion, it can be concluded that based on the MBV pu and TSV pu , the proposed topology offers good performance.

Comparison based on boosting capability
The boosting capability of a topology means that its peak value of output voltage is greater than the total supplied DC voltage. The ratio of V o,peak /V in,dc is termed as the boosting gain. The proposed topology has 1.6 gain in the output voltage. Only one other topology [34] has the boosting capability, but it utilizes 14 IGBTs to produce 13-level output. Moreover, it has higher TSV pu and MBV pu then the proposed topology. Thus, the proposed topology offers boosted output with reduced TSV pu and lower number of DC sources.

Comparison based on efficiency
For efficiency comparison, thermal modelling of the proposed and other compared topologies has been done in PLECS software. Figure 13(b) depicts the efficiency versus rated output power curve of the proposed topology and capacitor-based conventional topology, i.e. NPC and the topology presented in [34] at the same peak voltage at the output. It can be seen that the proposed topology performs better in terms of efficiency. Thus, the proposed topology is efficient and has a lower number of sources suitable for renewable energy applications. Thus, considering the comparative study above and the experimental as well as simulation analysis, following remarks regarding the problems solved by the proposed topology can be made: (a) The multi-level inverter's first and foremost problem is the trade-off between the better waveform, i.e. higher output levels and the lower device count. The proposed topology offers 17-level output with a lower number of devices used. As shown in Table 3, the topology offers 1.54 N L /N sw ratio. (b) Due to the voltage boosting ability, the topology reduces the number of DC sources required to produce a higher output. (c) The capacitors utilized are of smaller size and does not require any extra sensor to maintain the voltage stability; thus, control complexity is reduced.
Although there are various applications suitable for multilevel inverters such as Electric Vehicles [36], integration of solar panels into utility grid with MLI acting as interface [8] etc, considering the discussion above it is safe to say that the proposed topology is suitable for renewable energy applications, especially solar PV-based applications. Since the proposed topology is asymmetric, one of the main disadvantages is that it requires a large variety of DC sources in cascaded structures. A single cell, it utilizes two DC sources of different magnitudes. Two PV panels with MPPT can be used as two isolated DC sources for a single cell. In case the topology is utilized in cascaded structure, or a modular structure, a single input, multi-output DC-DC converters can be used to provide different sources of the same magnitude. This will require two DC-DC converters with multiple outputs to act as two different sources of magnitudes for different cascaded cells of the proposed topology. Figure 14 depicts the application of the proposed topology in single-cell operation and cascaded structure utilizing multiple output DC-DC converter.

CONCLUSION
This paper presents a new and improved topology to produce the 17-level boosted output with a gain of 1.6 in asymmetric mode. The topology offers lower TSV pu as well as utilizes a lower number of switches. The topology uses 11 switches with one switch being of bidirectional blocking and bidirectional conducting operation. The topology employs two DC sources in 2:3 ratio for asymmetric configuration along with three capacitors. The topology can also be used in the symmetric structure at the cost of a lower number of levels, i.e. producing 13-level output. The capacitor helps boost the number of levels through various combinations by a factor of 1.5 in symmetric mode and a factor of 1.6 in asymmetric DC combinations. The performance of the topology is proved to be satisfactory in static as well as in dynamic conditions. Experimental validation is done using the developed prototype. The promising results are obtained in the experimental setup. The topology is compared with other topologies to confirm the effectiveness and assert that the topology is suitable for the various medium-and high-power applications.