A novel transformerless high step-Up DC-DC converter with active switched-inductor and quasi-Z-source network

Conventional dc–dc boost converters have limited boosting capabilities, and the main switching device may suffer relatively high voltage stress and current stress. A novel transformerless dc-dc boost converter is proposed in this paper. The proposed topology, which combines the traditional active switch-inductor and quasi-Z-source network, can increase the voltage gain without limiting the duty cycle or increasing the voltage and current stresses of the power switches. The detailed analysis including working principles, steady-state characteristics, non-ideal element analysis and a comprehensive comparison is also presented in this paper. To verify the proposed converter’s performance, a prototype circuit with 20–30 V input voltage, 200 V output voltage, and 200 W output power is implemented in the laboratory. Experiment results conﬁrm the theoretical analysis and advantages of the proposed converter.


INTRODUCTION
A dc-dc converter with high step-up capability is used for many applications, such as distributed generation resources, hybrid electrical vehicles, battery backup systems for uninterruptible power supplies, and LED lighting systems. Generally, the conventional boost converter appears as a suitable candidate for these applications. However, the power device is subjected to high voltage stress and current stress, which will lead to high losses and serious reverse recovery problems [1]. As a result, its maximum voltage transfer ratio is only about five in practice, rather than infinity in theory. Many topologies have been proposed to improve the boost capabilities of the dc-dc converters, which can be generalized as the isolated type and non-isolated type. The isolated topologies, such as flyback, forward, push-pull, half-bridge, and fullbridge type, can increase the voltage gain by adjusting the turn ratio of the transformer [2,3]. However, the switches of these converters may suffer extremely high voltage spikes due to leakage inductance of the transformer. To resolve this problem, a snubber circuit [4] or clamping circuit [5] is often required. However, these techniques are complex with low efficiency or high cost. Moreover, transformer-isolated converters tend to be more expensive because of increasing manufacturing costs.
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology A transformerless dc-dc converter with a high step-up ability may be more attractive because of the lower cost and higher efficiency, which can be generalized as the coupled-inductor-based type [6,7] and noncoupled-inductor based type [8][9][10][11][12][13]. The coupled-inductor converters can achieve high step-up voltage gain and minimize the voltage stress on the power switch. However, compared to other structures, the converter is relatively bulky. Moreover, the problems mentioned in isolated topologies also exist for this type of converter. Many high step-up dc-dc converters without a coupled-inductor have been proposed. The focus of the research studies include the voltage-lift [8], cascade techniques [9], switched-inductor [10,11], switchedcapacitor [11,12] and impedance-network-based topologies [13][14][15].
The voltage-lift circuit is first proposed in [8], then by merging the main power switch, the relift circuit and triple-lift circuit with enhanced boost ability are also proposed. However, the voltage stress on the switch is relatively high, and the number of capacitors and semiconductors will increase as the voltage gain increases. A high voltage gain can also be obtained through the two cascaded boost converters. However, an additional power switch is required. The two switches are integrated into one in [9] to reduce circuit complexity and cost, but the drawbacks mentioned for [8] also exist for this converter. Although Quasi-Z-source dc-dc converter and active switched-inductor dc-dc converter. (a) Quasi-Z-source dc-dc converter [13]. (b)Traditional active switched-inductor dc-dc converter [10] the switched-capacitor and voltage-lift technique can achieve high voltage gain, the main switch suffers high transient current. Thus, the conduction loss is increased, and the efficiency has deteriorated. Impedance-network-based dc-dc converter is shown in Figure 1(a), which can achieve high voltage gain under lower duty ratio. However, its duty ratio is limited, and the power switch and diode may suffer relatively high voltage stress and current stress.
The active switched-inductor (ASL) dc-dc converter is first proposed in [10], as shown in Figure 1(b), compared to other structures, it has the following merits: (1) the charging currents of the inductors are divided between the two power switches. Thus, the conduction loss can be reduced; (2) compared with boost converter, the switch voltage stress is lower, so switches with low on-state resistance can be employed to improve the efficiency. However, the voltage gain is (1+D)/(1−D), which is not significantly improved compared to the traditional boost converter. In order to improve the converter boost capability, many ASL based converters have been proposed. For example, the voltage gain is improved by replacing the inductor with passive switched-inductor [16]. The proposed structure can also reduce the current stresses of the inductors. Besides, all the inductors in the proposed structure with the same inductance value share the same operation, which provides the potential to achieve magnetic integration. However, the output diode and power switch suffer increased voltage stresses, which will increase the probability of failure and cost. In [17] and [18], the proposed structures utilize switched-capacitor (SC) and ASL to improve the overall voltage gain. The proposed structure can also reduce the switch voltage stress under the same output condition. However, the capacitor voltage stress and diode voltage stress are relatively high, making it difficult for the proposed structure to achieve higher voltage conversion ratio by cascading SC cells. A novel switch-diode (SD)-box is proposed and applied in ASL topology in [19], compared with the converters proposed in [17] and [18], the proposed structure can adjust switch duty cycle more flexibly. What iss more, the SD-box can deal with problems caused by different inductance values. And similar structures also exist in [20]. However, for this type of converters, the maximum voltage gain of the converter is indeed not improved, and the voltage stress of the newly added switch is relatively high (equal to the output voltage). Besides, its control system has become more complicated.
A novel ASL based dc-dc converter is proposed in this paper. In the proposed structure, quasi-Z-source network (QZSN) and ASL are utilized to improve the overall voltage gain. And the high voltage gain is achieved without increasing the voltage stresses and current stresses of the power switches. Compared to other structures, the proposed structure can provide a higher voltage gain with the same duty ratio and achieve lower device voltage stress and device current stress under the same output condition. What is more, the proposed structure has the capability of adding extra stages to get higher voltage gain. The rest of this paper is constructed as follows. In Section 2, the structure of the proposed converter is proposed, and the circuit operation modes including continuous conduction mode (CCM) and discontinuous conduction mode (DCM) are analysed. In Section 3, the steady-state characteristics including voltage gain, device voltage stress, device current stress, boundary conditions and external characteristics are analysed. In Section 4, the voltage gain and converter efficiency considering non-ideal elements are calculated. In Section 5, the cascaded topology is proposed and analysed. In Section 6, a comprehensive comparison between the proposed and other converters is presented to show the proposed converter's advantages. In Section 7, the experimental results are provided to verify the theoretical analysis and practicality of the converter. In Section 8, the overall conclusion of this article is presented.

OPERATING PRINCIPLE OF THE PROPOSED CONVERTER
The circuit topology of the proposed converter is shown in Figure 2, which contains one active switch-inductor (L 1 -S 1 -L 2 -S 2 ) circuit and two quasi-Z-source networks (L 1 -C 1 -L 2 -C 2 -D 1 and L 3 -C 3 -L 4 -C 4 -D 2 ). Switches S 1 and S 2 are controlled simultaneously by using one control signal. Additionally, the proposed converter comprises an output diode D o , an output capacitor C o and load R.
The operating principles of CCM and DCM are analysed in this section. In the following analysis, the following assumptions are assumed. (1) All the capacitors are large enough. Thus, the voltage of the capacitors is considered as constant in one switching period. (2) The devices are ideal, and the parasitic elements are neglected. (3) Considering the symmetries of the proposed topologies, the inductors L 1 and L 2 possess the same level of inductance, the same applies to L 11 and L 21 . The typical waveforms for CCM and DCM are shown in Figure 4.

CCM operation
State 1 [t 0 -t 1 ]: Switches S 1 and S 2 are turned on, all diodes work in off-state. The current flow path is shown in Figure 3(a). L 1 and L 2 are charged by the dc source. L 11 is charged by the dc source and C 12 via C 11 , L 21 is charged by the dc source and C 22 via C 21 , the output capacitor C o provides its energy to load R. According to KVL, the voltages of the inductors can be expressed as : Switches S 1 and S 2 are turned off, all diodes work in on-state. The current flow path is shown in Figure 3(b). Inductors L 1 , L 2 , L 11 and L 21 are series-connected to charge the load and capacitor C o . C 12 and C 22 are charged by L 1 and L 2 respectively. According to KVL, the following relationships can be obtained Additionally, the following equations can be obtained due to the symmetries of the topology. {

DCM operation
State 1 [t 0 -t 1 ]: The equivalent circuit is similar to state 1 of the CCM operation. The difference is that the currents of L 11 and L 21 flow in both directions. During this time interval, i L11 and i L21 first fall from the reverse peak to zero, and then rise from zero to the forward peak.
The equivalent circuit is similar to state 2 of the CCM operation, but the currents of L 11 and L 21 still flow in both directions, which is similar to state 1. At the end of state 2, i L1 (i L2 ) and i L11 (i L21 ) possess the same amplitude but opposite directions, which can be expressed as : During this time interval, all switches and diodes work in off-state. The current flow path is shown in Figure 3(c). The currents of L 11 and L 21 flow in reverse. C o provides its energy to load R, L 1 and L 11 freewheel via C 11 and C 12 , L 2 and L 21 freewheel via C 21 and C 22 .

CCM operation
We assume that T 0 = DT S is the time interval of state 1, where D is the duty ratio, T 1 = (1−D) T S is the interval of state 2. By applying the voltage-second balance principle to the inductors, we obtain According to KVL and applying the calculated voltage relationships of capacitors, the voltage stress on the power switch (drain to source) and diodes (cathode to anode) can be calculated as The efficiency of the converter is assumed to be 100%. Then, the output current can be expressed by the average input current as The average current of the inductors is expressed by I L1 , I L2 , I L11 and I L21 respectively, the average current of D 1 , D 2 and D o is expressed by I D1 , I D2 and I Do respectively, and the average current of switches are expressed by I S1 and I S2 respectively. According to the charging balance of the capacitors, Equations (9) and (10) can be obtained. Besides, Figure 5 shows the average current equivalent circuit of the converter.

DCM operation
We assume that T 1 = DT S is the interval of state 1, T 2 = D M T S is the interval of state 2. Then the time corresponding to state 3 is The voltages across the capacitors as well as the output voltage U o can be expressed by From Equation (11), the voltage gain is expressed as Assuming L 1 = L 2 = L 0 , L 11 = L 21 = L, the average current of the inductors is given by Equation (13). From Figure 4(b), the average currents of the inductors during each switching period are given by Equation (14), according to Equation (12), D M can be rewritten as Equation (15) From Equations (13)-(15), the duty cycle D can be derived as Then, a dimensionless constant τ is defined as Substitute Equation (17) into Equation (16), the voltage gain is given by The curve of the voltage gain is shown in Figure 6. It can be seen the voltage gain in DCM operation will increase as τ decreases.

Boundary operating condition between CCM and DCM
We assume that the converter works under the boundary of DCM and CCM operation, the voltage gain of DCM operation is equal to that of CCM operation. The boundary dimensionless constant τ B can be derived as  The curve of τ B is shown in Figure 7. If τ is smaller than τ B , the proposed converter is operated in DCM operation.

External characteristic of the proposed converter
In order to represent the parameterized converter output current, a dimensionless parameter γ is defined as Suppose that the converter is operating under the boundary conditions of CCM and DCM. The following equation can be According to Equations (13)-(15), the voltage gain in DCM operation can be obtained as Combine Equations (21) and (22), the external characteristic of the proposed converter is depicted in Figure 8. The proposed converter will be more likely to work in DCM operation when D = 0.5.

NON-IDEAL ELEMENT ANALYSIS OF THE PROPOSED CONVERTER
The parasitic parameters of all elements are ignored in the above analysis. However, the losses of each component could influence the efficiency and boost ability of the proposed converters. In this section, the effects of non-ideal elements on the proposed converter are analysed. Also, the power loss, efficiency, and nonideal voltage gain expressions are calculated in detail. We assume the equivalent series resistance of the capacitors is r C , the forward voltage drops of the diodes are U D , the on-resistance of the switches is r S , the dc resistance of the inductors is r L and r L0 , Figure 9 shows the equivalent current loops of the proposed converter in CCM operation.

Power loss and efficiency
The power switch's conduction loss is related to the onresistance and root-mean-square (RMS) value of the switch According to Equations (8) and (23), the conduction losses of the switches can be calculated as The switching loss can be estimated by linearizing the current and voltage of the switches when they are changing the states [13], as Where U S is the voltage stress on the switch before it is turned on, I S is the current through the switch after it is turned on, f s is the switching frequency, t on is the turn-on delay of the switch. t off is the turn-off delay of the switch. Then, using Equations (24)-(26), the total power loss in the main switches can be calculated as follows The losses of the diodes depend on the magnitude of the current flow and their forward voltage drops. Therefore, the currents of diode D 1 and diode D 2 can be expressed as follows.
Substituting Equation (8) into (28), the power loss associated with the forward voltage drop U D is Consequently, the total power loss in the diodes is obtained by The losses of the inductors in the PWM converter are mainly the conduction loss. According to Equation (9), the conduction losses of the inductors are given by Then, the total power loss of the inductors is calculated as The capacitors' power losses depend on the equivalent series resistance of the capacitors and root-mean-square value of the currents. According to the charging balance of the capacitors, the currents passing through the capacitors can be approximated by According to Equations (34) and (35), the power losses of the capacitors can be obtained as Equation (36), then, the total power loss of the capacitors is calculated as Equation (37) We assume that the input voltage range is 20-30 V, the output power is 200 W, and the output voltage is 200 V. The power loss considering the nominal specifications and selected components (shown in Table 1) is calculated, shown in Figure 10. It can be seen the inductor loss presents the most significant impact on the power loss, followed by the diode loss and switch loss. This analysis proves that the overall efficiency can be improved by optimizing parasitic parameters.
The proposed converter efficiency η is calculated as The efficiency related to input voltage and duty cycle is shown in Figure 11, it can be seen that (1) for a constant duty ratio, the efficiency will increase as the input voltage U i increases; (2) for a constant input voltage, the efficiency will first increase and then decrease as the duty ratio increases.

Non-ideal voltage gain of the proposed converter
The ideal voltage gain of the proposed converter can be expressed as The non-ideal voltage gain will be decreased due to the limitation of parasitic parameters. But the current transfer function is true for ideal and non-ideal conditions, which can be Thus, the non-ideal voltage can be calculated as Average switch current stressI S1 , I S2 D + The voltage gain curve considering the selected components is shown in Figure 12. It can be seen the proposed converter can maintain a high boost capacity when G < 35. Also, the measured voltage gain for experiment matches well with the theoretical analysis.

EXTENSION OF THE PROPOSED CONVERTER
The cascaded topology is proposed in this section, which is obtained by cascading the multiple quasi-Z-source networks, as shown in Figure 13. N is an even number to maintain the symmetry of the topology. We assume that the proposed converter is operated in CCM operation. Using the same analysis method in Section 3, some steady-state characteristics can be obtained, which are summarized in Table 2. Since there are 3 diodes, 5 capacitors, 2 switches and 4 inductors in the basic structure, it is expected that there are N + 1 diodes, 2N + 1 capacitors, 2 switches and N + 2 inductors in the topology with N switchedcapacitor cells.
According to Table 2, the voltage stresses of the capacitors are decreased when increasing the number of quasi-Z-source networks. In addition, the current stresses of the inductance and diodes in the cascade QZSNs are relatively low (equal to the output current I o ), which can improve the efficiency and reduce the size.
To give a graphical presentation, Figure 14 is depicted, in which the voltage gain, device voltage stress and current ripple of the inductors are present to illustrate the characteristics of the cascaded topology. It can be seen that the cascaded circuit can achieve higher voltage gain with the same duty ratio, and the voltage stresses of switches and diodes as well as the current ripple of the inductors are reduced under the same output condition.

COMPARISON
This section compares the proposed converter with other existing transformerless high step-up converters. The comparisons are performed on their boost factors, component numbers, voltage stress and current stress on devices shown in Table 3. Besides, graphical comparisons are shown in Figure 15.
Generally speaking, compared with other high step-up dcdc converters, the proposed converter can provide higher voltage gain with the same duty ratio and maintain lower device voltage stress and device current stress under the same output  Maximum diode voltage stress condition. Although the impedance network based converter proposed in [14] and [15] can achieve high voltage gain at a lower duty ratio. Their duty ratio is limited, and the device voltage stress and device current stress are higher than other structures. Besides, the high voltage gain is achieved as the duty ratio reaches the D max boundary. Operating at such a high duty cycle will increase the current ripple and deteriorate the efficiency. As a result, the practical voltage boost capability of these two converters will be affected. Compared with the buck-boost quadric converter [21], the proposed converter can provide a higher voltage when D < 0.81. Besides, the proposed converter can achieve lower device voltage stress and total device current stress under the same output condition.
The Sepic-based high step-up dc-dc converter [22] can provide a higher voltage gain among the compared structures, and the total diode current stress and total inductor current stress are relatively low. Besides, the proposed structure is capable of achieving a higher voltage gain by adding extra stages. However, the capacitor voltage stress will increase as the number of stages increases. Compared to the Sepic-based high stepup dc-dc converter, the converter proposed in this article has lower capacitor voltage stress, resulting in lower cost and smaller size.
Among the compared structures, the switched-capacitor converter proposed in [23] can provide the same voltage gain with the lowest current and voltage stresses on power switches, and only one magnetic element is employed. However, its voltage gain is difficult to adjust (no less than 3, no more than 4), and one more switch is required. Also, if higher voltage gain is required, the number of stages will increase, resulting in an unexpected increase in the number of devices.

Parameter design
Assuming the maximum allowed current ripple of the inductance is x L %, inductance L 1 and L 2 can be designed as Where dt = DT S is the time interval when the switch S is turned on, and di L = x L %I L is the variation of the inductor current during this time interval. Similarly, the inductance L 11 and L 21 can be designed as If the proposed converter is designed to operate in DCM, the following equation can be obtained.
Taking the x C % peak-to-peak capacitor voltage ripple into consideration, the capacitance C o can be designed as Where dt = DT S is the time interval when the switch S is turned on, and du C = x C %U C is the voltage ripple of C o . Similarly, other capacitors can be designed as

Experiment results
A prototype of the proposed converter in Figure 2 is built to verify the proposed converter's operation principles and practical boost capacity. The experimental parameters are shown in Table 4. And the principle prototype is shown in Figure 16. Figure 17 shows some typical experimental waveforms under U in = 20 V. The operating duty ratio is 0.7, which is basically in line with the theoretical calculation value (D≈0.692). In addition, the measured voltage across C 11 and C 21 are 44.5 and 46.3V, respectively. Besides, the switch voltage stress u ds is 65 V. The diode voltage stresses U D1 and U Do are 65V and 130V, respectively. The average current of the diode D o is 1.03 A. The average currents of inductors L 1 and L 11 are 5.75 and 1.03 A, respectively. Besides, the experiment results for U in = 30 V are shown in Figure 18. The measured device voltage stress and device current stress of the components all match the theoretical analysis. Consequently, the correctness of the theoretical analysis is confirmed. Inductors L 11 /L 21 1 mH(CCM)/120 μH(DCM)

FIGURE 16
Principle prototype and its control circuit The experiment results for DCM operation under D = 0.25 are shown in Figure 19, the dimensionless constant τ and the voltage gain G under the selected parameters are calculated as τ = 0.011 and G = 5.37. The measured output voltage and voltage gain of the prototype are U o = 102 V and G = 5.1, respectively. Besides, it can be seen the inductor current i L1 and i L11 are equal and opposite in the freewheeling phase. Also, the experiment results for D = 0.4 are shown in Figure 20. Considering the inherent loss of the converter, the theoretical analysis is proved to be correct.
It is worth mentioning that the inductor current has a relatively low sinusoidal pulsation at state 3 (freewheeling phase), which is caused by the resonance between the inductors and the junction capacitance of the power semiconductors. And this resonance will not occur in either state 1 or state 2, because it can be suppressed by a complete capacitor loop in these two states. For example, in state 1, diode D 1 works in off-state, the voltage across D 1 is clamped by U in + U C12 . In state 2, switch S 1 works in off-state, the voltage across S 1 is also clamped by U in + U C12 . While in state 3, although both D 1 and S 1 work in off-state. There is no complete capacitor loop to clamp the voltage of the junction capacitance. Therefore, resonance will occur at this stage, as shown in Figure 19(b) and Figure 20(b). In Section 2, since all components' parasitic element is ignored, the amplitude of the resonance is equal to zero. Thus, the inductor current can be approximated as flat in the freewheeling phase.
The measured efficiency curve of the proposed converter under U o = 200 V is shown in Figure 21. It can be seen the efficiency is improved when increasing input voltage. Besides, the voltage gain-efficiency comparison is given in Table 5. Compared with other high step-up dc-dc converters with the same power level. The proposed converter can achieve higher efficiency with the same voltage gain.

CONCLUSION
This paper has proposed a novel transformerless high voltage gain dc-dc converter. By utilizing the active switched-inductor converter and quasi-Z-source network, the higher voltage gain is achieved without increasing the voltage stress on power switches and output diode. Circuit operation principles, steady-state analysis and nonideal elements analysis are presented. It was seen that the working mode of the proposed converter is similar to that of cuk dc-dc converter. The discontinuous conduction mode refers to the diodes D 1 and D 2 which are turned off in state 3, rather than a discontinuous current of the inductor.
The cascaded topology was proposed in Section 5. Some desirable features exist in the cascaded topology, such as higher voltage gain, lower device voltage stress and lower current ripple of the inductors.
A comparison considering the proposed and other structures was also provided. Considering the results, the superiority compared to other converters is confirmed.
Finally, experimental results were given to verify the characteristics of the converter and theoretical analysis. Considering the approved advantages, such as high voltage gain, high efficiency, and low device voltage stress and current stress, it could be a suitable choice for uninterruptible power supply systems, LED lighting systems, fuel cells, and electric vehicles, where high voltage gain is often required.