A hybrid switched inductor with ﬂexible high voltage gain boost converter for DC micro-grid application

A hybrid switched inductor with ﬂexible high voltage gain boost converter for 400 V DC microgrid application is presented in the paper. The three operating modes of the converter are controlled using three switches by two-duty ratios. The proposed converter provides ﬂexibility in the selection of the duty cycle to achieve desired output voltage. Moreover, with two duty ratio, high gain with a wide duty range is accomplished in the proposed converter while an individual switch does not need to operate at a very large duty ratio. The power circuit analysis, operating principles, steady-state voltage gain analysis during continuous conduction mode (CCM) and discontinuous continuous mode (DCM), boundary condition, efﬁciency analysis, comparison, and circuit parameter design of the proposed are presented. A closed-loop controller design and small-signal modeling are discussed. The dynamic behavior of the proposed converter is validated with a change in duty ratio, input voltage, and load power. A laboratory prototype converter is designed and developed to verify the model, and feasibility of different operation modes. The prototype is tested for a power range of 100 W–500 W for different duty cycles.


INTRODUCTION
From the last decade, the DC microgrid has been continuously gaining attention due to the penetration of RES in the distributed generation energy system with the help of power electronics converters. However, the DC microgrid system is mainly powered through Photovoltaic (PV), Fuel Cell (FC), or Energy Storage System (ESS)/batteries through power conversion units [1,2]. Therefore, the number of PV or FC can be connected in series or in parallel connection to meet the load demand. However, it is not a viable solution that results in lower efficiency and also requires large space for the installation and has higher cost. Therefore, to overcome this shortcoming, a high gain, efficient, and high power density DC-DC converter is accommodated at the source end in the microgrid system [3,4]. In literature, numerous non-isolated converters based on the switched inductor, switched capacitor, voltage multiplier etc. are addressed to achieve high gain [7,12]. In order to achieve high voltage, operating a conventional boost converter with a high duty ratio causes several issues such as diode reverse recovery problem, increased level of switching losses, impaired tran-This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology sient response, high voltage/current spikes, and low efficiency [13,14].
In cascaded and quadratic boost converter, more components are required to achieve high voltage gain, which increases the complexity and results in poor efficiency. The converters employing switched capacitor circuits for achieving high gain can easily boost up the voltage according to the number of Switched Capacitor (SC) cell [9,12]. These converters do not need any inductive element; however, the main drawbacks concerned with these topologies are ripples in input current, poor voltage regulation during wide load variations, and the required large number of capacitors. The Voltage Multiplier (VM) based DC-DC converters have a modular structure, reduced voltage stress across the switch along high voltage gain. The high capacitor charging transient current and power handling capability of VM capacitors are the major drawbacks associated with VMbased DC-DC converter. However, these boosting techniques increase the complexity, cost, and affect the efficiency of the system. In [15], three different configurations (namely converter I, II, and III) have been presented by modifying the switched inductor boost converter. With the help of two switches, the switch current stress and conduction loss caused by switched inductors have been overcome. Further, this converter is extended by the addition of diode and capacitor structure to extend the voltage gain. However, in these converters, both switches are controlled with a single-duty ratio. Therefore, the voltage gain of converter-I, II, and III is restricted due to the limitation of duty ratio alike traditional boost converter. Moreover, the shortcomings of [15] converter configurations have been overcome by a non-isolated step-up converter as given in [16] by adding one additional unidirectional controlled switch.
In the [16] converter, the voltage gain has been increased with the adjustment of the two-duty ratio. With the addition of one extra diode and capacitor in the [16] converter, the voltage has been increased and can be controlled in a wide duty range in Double Duty Triple Mode (DDTM) converter as presented in [17]. With the same number of components as in [17] converter with the proper arrangement, the voltage gain of [17] converter has been boosted as presented in [18]. Furthermore, the use of more diodes leads to an increase in the instantaneous power loss by the diodes, needing additional heat sinks. The increased switching frequency significantly increases the switching power loss in the switching devices. In [16,18], the load side switch is connected with a diode to evade the reverse current flow and short circuit of input supply. With this arrangement, the switching operation of the load side switch is dependent on the seriesconnected diode. Therefore, this can obstruct the performance of the converter at higher frequencies [19]. However, from [16,17], it is noticed that the diodes of power circuitry have more contribution to power loss as compared to switches and also affecting the and directly affects the efficiency of the converter.
This article presents a new transformer-less high gain boost converter to achieve high voltage gain with a reduced number of diodes at a lower duty range as compared to the discussed converter. Additionally, the advantage of the proposed converter are: (1) the high duty ratio limitation is overcome by controlling three switches with two distinct duty pulses, (2) continuous input current, (3) current stress of three switches can be controlled optimally with the additional degree of freedom introduced by the two duty pulses, and 4) The lowest average voltage stress on switches and higher efficiency as compared to the converter in [16,17]. Figure 1 shows the power circuit topology of the proposed converter. The proposed power circuitry is derived with two inductors (LX, LY), two capacitors (C 1 , C 0 ), three power MOSFETs (SX, SY, SZ), and one diode D0. The inductance value of both the inductors LX and LY are the same; hence, LX = LY = L. In the proposed converter, both switches (SX, SY) operate in synchronization and are controlled by a single gate pulse (k1), whereas switch (SZ) is operated through gate pulse (k2) with the delay of k1TS.

CCM operation
The proposed converter has two different duty pulses, which indicates that the converter operates in three different modes as CCMI (0 to k1TS), CCMII (k1TS to k2TS), and CCMIII (k2TS to TS) in CCM.

CCM I (0 to k 1 T S )
In this mode, switch SX and SY are turned ON and its corresponding circuitry is illustrated in Figure 2(a). The input voltage supply is in parallel with both inductor (LX and LY) and capacitor C1. Therefore, capacitor C1 charges through switch SY and diode DZ (antiparallel diode of switch SZ) with the current path as Vin-SY-C1-DZ-SX-Vin. Capacitor C 0 reverse bias the diode D 0 continuously delivering its energy to the resistive load (R) as illustrated in Figure 2(a). The equivalent inductor and capacitor voltages in CCMI is express as 2.1.2 CCM II (k 1 T S to k 2 T S ) In this mode, switch SZ is in conducting state and its corresponding circuitry is illustrated in Figure 2(b). The inductors (LX and LY) and capacitor C1 are in series with input supply (Vin). Therefore, switch SZ allows both inductor LX and LY to be serially magnetized from the series combination of input supply (Vin) and capacitor C1 (Vin-LXSZ-C1-LY-Vin). The capacitor C 0 continuously supplies the energy to the resistive load. Therefore, the following equation can be written: 2.1.3 CCM III (k 2 T S to T S ) In CCMIII, three switches (SX, SY, and SZ) are turned OFF and their corresponding circuit is illustrated in Figure 2(c). The inductors and capacitor C1 are in series connection with input supply along with capacitor C 0 . Therefore, inductors and capacitor C1 demagnetize/discharge to charge the capacitor C 0 and deliver energy to the load (V in -LX-D 0 -C 0 /R-C1-LY-V in ). Therefore, the following equation can be written as By applying the inductor voltage second balance principle for inductor LX, the resultant output voltage of the proposed converter in CCM is expressed as Figure 3 illustrates the characteristics waveform of the proposed converter in CCM in ideal condition. From (4), It is noted that the proposed converter operates with very few limitations as, at the same time, both duty ratio (k 1 and k 2 ) should not be equal to 0.5. The addition of both should, however, not be more than one. Figure 4 illustrates the voltage gain curve MBC-AG with different duty ratio (k 1 , k 2 ). It is noted that for a different combination, the maximum voltage gain obtained from the proposed converter is 40 with an ailment of (k 1 +k 2 = 0.95).

DCM operation
The proposed converter can be operated in DCM mode either by change in load value, switching frequency, or inductance. The proposed converter has four operating modes in DCM operation, out of which the first two modes are similar to the CCM operation. The third mode of CCM ends when the inductor current reaches zero at (k3) and the fourth mode will start after the end of the third mode. The switching diagram of DCMIV is shown in Figure 5(a) and the characteristics waveform in DCM is shown in Figure 5(b). The equivalent current equations in all  four modes can be calculated as In DCM IV , the energy stored in capacitor C 0 is discharged to the load. Therefore, from (5)- (7), Therefore, the average capacitor C 0 current can be expressed as follows: where i C0 is the current through capacitor C 0 . In the steadystate condition, the average current through capacitor C 0 is zero. Hence, Using (9), the voltage gain of the proposed converter in DCM mode is derived as where τ L is the generalized inductor time constant. Figure 6(a) shows the voltage gain of the proposed converter in DCM modes at different duty ratio. Using (4) and (11), the boundary for CCM and DCM can be obtained as follows: where, τ B is boundary normalized inductor time constant. The curve of τ B versus duty cycles is shown in Figure 6(b). In this graph, the part above each curve indicates the CCM area of the proposed converter at that particular duty ratio, whereas, the area below the curve indicates the DCM part of the proposed converter. When τ B is higher than τ L , then the proposed converter operates in DCM. Nevertheless, the condition to operate converter in CCM is as follows: ( Figure 7 illustrates the circuit of the proposed converter with the ESR of components. In Figure 7, RLX, RLY, RC1, and RC0 represent ESR of inductor LX, LY, capacitor C 1 , and C 0 , respectively. RX, RY, and RZ are the ON-state resistance of switches SX, SY, and SZ, respectively. Diode D0 is replaced with their internal resistance R D0 and forward blocking voltage V F0 . Therefore, the related voltage and current non-ideal equations

EFFICIENCY ANALYSIS OF PROPOSED CONVERTER
Therefore, the resultant output voltage of the proposed converter is where The voltage drop contributed by each circuit component is presented in (18)- (20). It is worth noting that the voltage gain of the proposed converter is limited by ON-state resistance of switches and diodes, ESR of inductors, and capacitors. The input and output power of the proposed converter is derived as where P SW is switching losses by each switch and it is obtained by where VSX, VSY, VSZ, and ISX, ISY, ISZ are the average voltage and current across/through switches SX, SY, and SZ, respectively. Whereas, trX, trY, and trZ; and tfX, tfY, tfZ are the rising and falling time for the switches SX, SY, and SZ, respectively. Therefore, the efficiency of the proposed converter can be obtained by .

COMPARATIVE ANALYSIS
To summarize the advantageous features of the proposed converter, it is compared with the recently published high voltage gain topologies and gathered in Table I. It is noticed that the traditional boost converter is controlled through single-duty pulses, whereas, the voltage gain is restricted by ESR and diode recovery issues. However, by adding switched inductor structure [15] and using several capacitors [12], the voltage gain of boost converter has been increased. However, the voltage gain is not improved substantially with multiple capacitors and inductors.
With two inductors and two switches operated by a single duty ratio, three different configurations have been presented in [15]. However, in disregard of two switches and two inductors, the voltage gain of the converters presented is not high. Moreover, it can be seen that the voltage gain of [12,15] configurations are controlled with single duty ratio and cannot be worked within a wide range of duty cycles. In [16], an extra switch converter is added to increase the output voltage. These three switches, however, are operated by two distinct duty ratios, offering versatility in the choice of the duty ratio and overcoming the duty ratio cap. Moreover, to address the shortcoming of these converters, a DDTM converter topology has been presented in [17]. The voltage gain of the DDTM converter is significantly increased with the addition of two more capacitors and two diodes as compared to [17], whereas the voltage gain of [16] and [17] are not equally dependent on both duty ratios. The voltage gain of [16] is more dependent on the first duty ratio, whereas the gain of [17] on the second duty ratio. The voltage gain of the proposed converter is the same as the gain of [18] converter with a reduced number of diodes. In [18], the switching operation of switch SZ is dependent on diode D2 as both are connected in series. However, the capacitor C1 charging current has to pass through diode D1. Hence, diode D1 also contributes to countable power loss in an overall loss. So, it is worth noting that, the voltage gain of the proposed converter is comparatively high as compared to discussed high gain converters and equal to converter-I. Figure 8 represents the curve of change in voltage gain with respect to the duty ratio.
Besides, the high output voltage can be achieved with a minimum number of components as observed from Table I. From Figure 3, it is noted that the duration of voltage stress across three switches is short as compared to [15,17] at the same duty ratios. In the [20] converter, the voltage gain is high as compared to the proposed converter with the compromise of more number components. Also, the current stress of the switches increases along with the voltage gain. The reported efficiency is 94.6% at 500 W which is lower due to the more components. It also observed from Table I, the current stress of the switches is lower as compared to the other converter and equal to the converters of [17,18]. In the proposed converter, the voltage gain equally depends on both duty ratio, therefore no restriction on adjustment of duty ratio.

4.1
Parameter design

Inductor (L X and L Y ) design
The inductor value is selected on the basis of the average value of the charging current, its ripples, duty ratio, and switching frequency. Both inductors with an equivalent inductance (LX = LY = L) may be selected based on the operating principle. Therefore, for the CCM operation of the proposed converter, the critical values of each inductor can be calculated as where the values of ripple currents for the inductors LX/Y are indicated by ΔiLX/Y, respectively. For good estimation, the value of inductor ripple current (ΔiLX/Y) is selected between 20% and 40% of the average inductor current.

Capacitor (C 0 and C 1 ) design
The capacitor value is controlled by its charging current, the voltage ripple across it, duty ratio, and switching frequency. During CCMI, the capacitor C1 is being charged and being discharged during CCMII and CCMIII with a value of current equal to Iin. Thus, the capacitor voltage ripple for C1 can be obtained as follows: where ΔVC1 is the voltage ripple contents of the capacitors C1 and iin is the input current. The capacitors C 0 are discharged in CCMI and CCMII with a value of current equal to i 0 . Thus, the capacitor voltage ripple for C 0 can be obtained as where ΔV C0 is the voltage ripple contents of the capacitors C 0 and i 0 is the output current. For good estimation, the value of capacitor ripple voltage (ΔV C0 /1) is selected within 1% of the respective capacitor voltage with a voltage rating given by (1).

Switches (S X , S Y , and S Z ) and diodes selection
From the analysis and Figure 3, the voltage stress across switches (SX, SY, and SZ) are expressed as Therefore, switches should be selected with reverse blocking capacity as below However, diode D0 handles the Peak Inverse Voltage (PIV) equal to the output voltage (V0) in CCMI and CCMII as observed from Figure 3. Therefore, diode D0 should be select with PIV handling capability more than the output voltage. (29)

FIGURE 9
Closed controller logic of the proposed converter

Closed-loop controller
The dynamic response of the converter is observed with respect to change in input quantity as (a) change in input voltage, (b) change in load, and (c) change in duty ratio. The control objective in this converter is to control the output voltage during perturbations in input voltage, output resistance, and duty ratio. Unlike other DC-DC converters consisting of only one switch, the proposed converter consists of three switches (S X , S Y , and S Z ). As switches S X and S Y are switched simultaneously, the number of switches to be controlled is reduced to two. Conditions governing the control algorithm are given below: a. The duty cycle of the two switches must follow the inequality (S X,Y +S Z ≤1), as power stored in the charged inductors is supplied to the load only when all the switches are open. Thus, the sum of two duty cycles must never be greater than 1.0. b. Depending upon the operating mode, that is, S x,y < S Z or S x,y > S Z saturation limits of the two duty cycles must be appropriately selected. c. There are three states in a switching cycle operation. Switch S Z must be turned ON just before switches S x and S y have been turned OFF.
Considering these constraints, the two duty cycles are dependent upon each other. Thus, only one control loop is required to achieve the closed-loop performance of the converter. The other duty cycle can be determined by using the lookup table based on the recorded steady-state performance of the converter.
With the above-discussed strategy, the control algorithm is shown in Figure 9. Error obtained by subtracting output voltage reference with actual output voltage is represented by e(t). This error is passed through PI controller block to generate a X 1 (t) which will be passed through lookup table to generate a signal of X 2 (t). Both the constant value signal X 1 (t) and X 1 (t)+X 2 (t) are compared with carrier signal of 50 kHz frequency to generate the duty cycles. The respective duty pulses of both switches are obtained by doing the XOR logic operation as shown in Figure 9.

Small signal modelling of the proposed converter
The state-space matrix of the proposed converter in CCM I , CCM II , and CCM III can be obtained as follows: To obtain the average state-space model of the proposed converter, these three modes are combined by means of respective duty ratio (k 1 and k 2 ). The respective coefficients are When a disturbance occurs or is introduced (perturbations), the system response consists of a steady-state part and a transient part. After introducing the perturbations, the obtained system is having two components as the DC part and the AC part obtained by (34). The state-space model of proposed converter in terms of the control parameter (output voltage and duty ratio) is obtained as By controlling only duty ratio (k 1 ) and respective control logic between duty ratio (k 1 and k 2 ), the state-space model of the proposed converter with only duty ratio (k 1 ) is obtained as

FIGURE 10
Hardware prototype of the proposed converter The transfer function of the system can be obtained from the relation TF = C(SI-A) −1 B. The matrix form between the output voltage and duty ratio is obtained as follows:

HARDWARE RESULT DISCUSSION
A 500 W laboratory prototype of the proposed converter is developed to validate the theoretical analysis as shown in Figure 10. A list of specifications for the different circuit components of the prototype is presented in Table 2. The two gate pulses are generated through Virtex-5 FPGA with a 50% duty cycle (k1) to control switches SX and SY. Also, the gate pulse with a 35% duty cycle is generated to control switch SZ with a delay of the ON period of switch SX and SY. Figure 11(a) illustrates the waveform of input-output voltage and current at k1 = 0.5 and k2 = 0.35. The proposed converter achieves 400 V at the output from 31 V input voltage. It can be seen that input current is having highest peak value in CCMI as it addition of both inductor current and capacitor C1 current. The inductors and capacitor C 1 current is equal to input current in CCMII with same positive slope as in CCMI, whereas in CCMIII, with a negative current slope, the input current begins to decrease as both inductors and capacitor begin demagnetizing/discharging in the load. The average values of output voltage and output current are observed as 400 V and 1.26 A, while the input voltage with non-ideality and input current average values are observed as 31 V and 16.93 A. It is worth to note that the proposed converter operate with 96% efficiency at 500 W power. Figure 11(b) depicts the waveform of output voltage (V0), inductor LX current (iLX), inductor LY current (iLY), and input current (iin). Both the inductors are magnetized in CCM I and CCM III ; therefore, both inductors have a positive charging slope in CCMI and CCMII and a negative slope in CCMIII. The experimentally observed average inductor (LX and LY) currents are 8.3 and 8.4 A, respectively. Figure 11(c) depicts the waveform of the inductor's current and voltage. Both inductors are individually charged with 31 V in CCMI and CCMII. On the other hand, the voltages across both inductors in the CCMIII are equal to (−169 V). Slight fluctuations are observed in both inductor voltage waveforms in CCMIII due to unequal voltage sharing of input and capacitor C1 between both inductors along with the slight practical difference in inductor ESR. Figure 12(a) illustrates the waveform of voltage across switches (drain to source). It is noticed that the maximum voltage stress across switch SX and SY is (200 V) in CCMIII only. Similarly, switch SZ handles 400 V (V0) in CCMIII only. Figure 12(b) shows the dynamic behaviour of the proposed converter with a change in duty ratio k2 from 0.35 to 0.2 while k1 = 0.5. It is worth noting from experimentally obtained results, the proposed system giving stable output voltage and current and regulating for the entire range of duty ratio. Figure 12(c) depicts the experimental efficiency of the proposed converter at different power with different duty ratios and at constant load. It is noted that 96.1% efficiency is achieved at 500 W power. From Figure 12(d), it is observed that the proposed converter effectively works and is regulated for the entire range of duty ratio. With the help of (28) and (29), the power loss distribution across each component in the proposed converter is graphically represented in Figure 12(d) at k 1 = 0.5 and k 2 = 0.35 with consideration of R LX/Y = 200 mΩ, R C1/0 = 200 mΩ, R SX/Y/Z = 65 mΩ, R D0 = 0.01 Ω, and V F0 = 0.8 V. It is investigated that three switches have more loss contribution as compared to other components, whereas output capacitor C 0 has less contribution to power losses.
To validate and check the dynamic response of the proposed converter under a change in input voltage (V in ), and load power (P 0 ), two tests are conducted by adding an input capacitor at the source end to reduce the input current ripple as below.

Test I: Response under input voltage (V in ) perturbation
To observe the dynamic performance of the proposed converter with perturbation in input voltage, the input voltage with perturbation of (31 to 26.5 V) is applied to the system and the reference output voltage set to +400 V. The experimental results obtained under test-I are shown in Figure 13(a) which shows the input voltage (V in ), input current (i in ), output voltage (V 0 ) and output current (I 0 ) waveform with perturbed input voltage. It is observed that a constant of 400 V is achieved at the output even though input voltage is varied from 31 to 26.5 V. Moreover, to support the investigation, input current (i in ) and output current (i 0 ) are also shown. From the input current waveform, it is investigated that, the mean value of input current is increased in corresponding to decrease in input voltage to maintain the power equality at input and output side. To maintain the constant output voltage with respective changes in input voltage, the duty cycle (k 1 and k 2 ) needs to be adjusted by the PI controller according to the error signal.

6.2
Test II: Response under perturbation of load power Figure 13(b) depicted the output voltage (V 0 ), input voltage (V in ), output current (i 0 ), and input current (i in ) waveforms when load power (P 0 ) changes. It is observed that the constant output voltage 400 V is achieved from 31 V even power changed. The input and output current changed accordingly to satisfy the power balance at the input and output side.

CONCLUSION
For 400 V DC microgrid applications, a new transformer-less modified boost converter with an adjustable voltage gain at a wide range of duty ratios is presented. The high voltage gain is achieved with the fine adjustment of two separate duty ratios without the use of the high duty ratio for the individual switch. The waveform of the CCM and DCM characteristics is studied and the CCM-DCM boundary is elaborated in detail in efficiency analysis. It is worth noting that, with a minimal number of components, the proposed converter provides high voltage gain and reduces voltage stress through switches and diodes. Therefore, for low to high voltage DC microgrid applications, the proposed converter offers a viable solution. The proposed converter provides high voltage gain with a wide duty range with the modification of two separate duty pulses, which is not possible with a DC-DC converter with a single switch. Also, the voltage conversion is equally dependent on both the duty ratios. From the experimental results, it concludes that the proposed converter work with 96.1% efficiency at k1 = 0.5 k2 = 0.35 for a power rating of 500 W. However, additional switch SZ has more contribution to power loss as compared to other components. The experimental results confirm the theoretical analysis, feasibility, and performance of the proposed converter.
solely the responsibility of the authors. The APC is funded by the Qatar National Library.