High-frequency single-switch PFC with frequency-modulation controlled class-E 2 converter

This paper presents a single-switch zero-voltage switching (ZVS) power-factor correction converter based on the class-E 2 converter at 1 MHz switching frequency. A design method for ensuring the ZVS for the entire line-voltage period is proposed. By visualising the ZVS region in the parameter space, circuit parameters can be easily obtained to achieve the ZVS for the entire line-voltage period. Additionally, a closed-loop controller is applied for achieving a high power factor, low total harmonic distortion of the input current and output voltage regulation. The experimental circuit achieved the ZVS in the entire line-voltage period against load variations. As a result, the implemented converter achieved the same level of power-conversion efﬁciency as the 100-kHz power-factor correction converters and a high power factor with low total harmonic distortion, which denoted the effectiveness of the proposed design method.

A high-frequency operation is required for the resonant single-stage AC-DC converter for reducing the circuit volume as much as possible. The class-E 2 converter [32][33][34][35][36][37], one of the typical resonant converters, is a leading candidate for highfrequency resonant AC-DC converters. Compared with the LLC converter, the class-E 2 converter has no high-side switch, It is expected to realise the single-stage AC-DC resonant converters with megahertz-order operation by applying the class-E 2 converters.
The class-E AC-DC converters work at several hundredkilohertz frequencies in previous researches [7,8,16,21]. In these papers, the class-E AC-DC converters were designed with the fixed input voltage and the rated load resistance as a DC-DC converter in the steady-state. However, the input voltage of the AC-DC converter varies with line frequency, which is much lower than the switching frequency, and the cutoff frequency of the output filter is determined by the line frequency. Namely, the class-E AC-DC converter always works in the transient state in the time range of the switching period, and the mismatch occurs with the design assumption. As a result, the switching losses occurred at a certain angular displacement range in the line-voltage period. This switching loss can be ignored at a 100-kHz switching frequency but cannot be done at megahertz operation. Therefore, it is necessary to establish the design method of the AC-DC converter for ensuring the zero-voltage switching (ZVS) operation in the entire range of the line-voltage period for achieving megahertz frequency operation.
This paper, which is the extended version of [32] 1 , presents a single-switch ZVS PFC converter based on the class-E 2 converter at one megahertz switching frequency. A design method for ensuring the ZVS for the entire line-voltage period is proposed. By visualising the ZVS region in the parameter space, we can easily obtain the circuit parameters to achieve the ZVS for the entire line-voltage period. Additionally, we adopt a closedloop controller for achieving a high power factor (PF), low total harmonic distortion (THD) of the input current, and output voltage regulation. The experimental circuit achieved the ZVS in the entire line-voltage period against load variations. As a result, the implemented converter, which is designed for battery charger application, achieved the same level of powerconversion efficiency as the 100-kHz PFC converters and a high PF with low THD. The effectiveness of the proposed design method could be confirmed from the experimental results.

2.1
Circuit topology and operation principle Figure 1 shows a topology of the proposed AC-DC converter.
The system includes the input stage and the class-E 2 converter, which consists of the class-E inverter and the class-E rectifier connected in series. This system converts the input ac line voltage into the DC voltage via the class-E 2 converter, whose switching frequency is much higher than the line frequency. Figure 2 shows example waveforms of the proposed converter in the line-voltage-period domain and switching-period domain, where L = 2 f L t and S = 2 f S t are phase displacements with the line frequency f L and the switching frequency f S , respectively.

Input stage
The input of the system is the sinusoidal voltage with line frequency f L , which is where V m is the amplitude, V I is the RMS value of the input AC voltage. The input-stage circuit consists of a rectifying bridge, as shown in Figure 1. The rectifying bridge generates absolutevalued sinusoidal voltage v B , as shown in Figure 2(a), which becomes the input voltage of the class-E inverter.

2.1.2
Class-e inverter The class-E inverter has input inductance L C , FET S , shunt capacitance C S , and resonant circuit L 0 -C 0 , as shown in There is only one source-grounded FET in the class-E inverter, and there is no source-floating FET. Therefore, the gate driver circuit becomes simple, which is one of the benefits of the class-E inverter for high-frequency operations.
The switching frequency of the class-E inverter is much higher than the input line frequency. Therefore, the output voltage of the rectifying bridge v B looks constant within one switching period of the class-E inverter, as shown in Figure 2(b). Besides, the input inductance L C is sufficiently high that the input current of the class-E inverter i C is regarded as DC current in one switching period.
The switching device S turns on and off periodically with switching frequency and the on-duty ratio D S . Because of the shunt capacitance C S , the pulse-type shape of voltage appears across the switch when the switch is in the off-state. For the class-E inverter, there are particular switching conditions when the FET turns on, which are v S (2 ) = 0, The conditions in Equations (2) and (3) are called class-E ZVS and zero-derivative switching (ZDS) conditions. When the switching voltage satisfies the class-E ZVS/ZDS conditions, the converter operates at the "nominal state." The switching frequency for satisfying the class-E ZVS/ZDS conditions is defined as nominal switching frequency f Sn . The converter, however, does not achieve the class-E ZVS/ZDS conditions when the converter parameters vary from the nominal conditions. The detailed discussion of the switching patterns was done in [38]. At outside of the nominal state, there are two switching modes. One is the ZVS, which can be achieved with the help of the FET body diode. The other one is the non-ZVS, which deteriorates the power-conversion efficiency at high frequencies, in particular.
Due to the L 0 -C 0 resonant filter, the resonant-frequency component f 0 = 1∕(2 √ L 0 C 0 ) of the switch voltage is extracted. Therefore, the current flowing through the resonant filter i L0 is nearly a sinusoid, which becomes the input current of the class-E rectifier.

2.1.3
Class-E rectifier The class-E rectifier consists of rectifying diode D, shunt capacitance C D , and L F -C F low-pass filter. The load device is represented by the load resistance R L . As shown in Figure 2(b), the waveforms of the class-E rectifier have the time-reversed duality of the class-E inverter. Namely, the rectifier diode can also achieve class-E ZVS/ZDS conditions when the diode turns off.
In the class-E diode rectifier, the class-E ZVS/ZDS are always achieved against parameter variations. Instead, the duty ratio of the rectifying diode changes accordingly. The DC output voltage of the system is V O , which can be obtained as an average value of the diode voltage in the line-voltage period because the cutoff frequency of the low-pass filter f C = 1∕(2 √ L F C F ) removes both the switching and the line frequency components.

Assumptions
The steady-state analysis is often applied for the class-E 2 converters [36,38]. The class-E 2 AC-DC converter proposed in this paper works in the time range of switching period. It is difficult to derive the theoretical steady-state waveforms of the line-voltage-period domain. In this paper, numerical analysis is adopted for the proposed converter.
Because of the coexistence of high switching frequency and low line frequency, the system becomes stiff. Therefore, the step interval should be small to derive the waveforms numerically. In this paper, we analyse the converter by the equivalent ideal model and the self-developed numerical program for computation-cost reduction. Figure 3 shows the equivalent model of the proposed converter. For simplifying the converter model, the following assumptions are given.
1. All the passive components work linearly.
2. The bridge rectifier B r is modelled by the ideal switches and on-resistances r DB . Therefore, the input stage is expressed by the voltage source v B and the diode on-resistance r B = 2r DB , which are connected in series, as shown in Figure 3(a). The input voltage v B is derived as: 3. The FET with its body diode is modelled by ideal switches, resistances, and voltage source, as shown in Figure 3(b), where r DS is the FET on-resistance, V SD is the forward voltage of the body diode, and r SD is the on-resistance of the body diode.

Circuit parameters and system equations
The numerical analysis model is formulated with the normalised variables and parameters. The converter characteristics can be discussed with a generality because of the dimensionless space. Namely, the obtained results are independent of switching frequency, input voltage amplitude, and load resistance. Now, we define the following dimensionless parameters: means a normalised resistance parameter, for example, LC = r LC ∕R Lr . By using these parameters, the circuit equations can be formulated as where the superscript "*" denotes a normalised variable. All the voltages are normalised by the RMS value of the input voltage V I , for example, v * S = v S ∕V I . Besides, all the currents are normalised by V I and rated load resistance R Lr , for example, In Equation (5), resistances of the switch S and the diode respectively.

Program execution and computation cost
By applying our differential equation solver, whose algorithm is based on the Runge-Kutta method, the transient waveforms of converters can be derived. We execute the program for 0 < L < 100 . It is regarded that the numerical waveforms are in the steady-state at L = 100 .
Performances of commercial software PSPICE and the selfdevelopment program are compared in the same environment. Computation times of the PSPICE simulator and our program are 21,920 and 1688 s, respectively, for L = 100 . The computation cost can be dramatically reduced because of the simplified circuit model and self-development numerical program.

Frequency modulation control
Generally, the output voltage of the class-E 2 converter is proportional to the input voltage in the steady-state operation. In the proposed AC-DC converter, however, the cutoff frequency of the rectifier is tuned to the line frequency. Therefore, the output voltage does not follow the variation of v B . As a result, the class-E 2 converter works in the transient state in the time range of the switching period. Namely, the equivalent input resistance of the class-E 2 converter is not constant in the line-voltageperiod domain. Figure 5 shows an example of numerical waveforms of the proposed converter with and without input current control. In the case of no input-current control, the input current distorts like a square wave, which means high-order harmonics are included in the input current. It is necessary to meet the restrictions on THD of the input current, such as the IEC-61000-3-2 [40].
On the other hand, the output voltage depends on the load resistance. For example, the output voltage increases as load resistance increases. For regulating the output voltage against load variations, a specific control needs to be applied.
For achieving PF correction, THD reduction, and output voltage regulation, a double-input single-output controller is adopted in the proposed system. There are two loops in the control structure. The inner loop shapes the sinusoidal input current with fast dynamics. The outer loop regulates the output voltage against load variations with a large time constant [41]. The switching frequency of the class-E 2 converter is determined by the controller.

4.2
Control circuit Figure 1 includes the control circuit. In this research, the digital signal processor (DSP) is adopted as the controller, whose maximum input voltage is V DD . The output of the DSP is the squarewaveform driving signal D r with frequency f S and fixed on-duty ratio D S , which is the input of the gate driver. It is necessary to sense output voltage v O , inverter input voltage v B , and inputinductance current i C determining the switching frequency in the DSP. The output voltage v O is scaled into v OS by the voltage-divider resistances r O1 and r O2 . Because v OS should be less than V DD , r O1 and r O2 should be chosen to satisfy where V Or is the rated output voltage, and < 1 is a coefficient for keeping a margin against V DD . The inverter input voltage v B is scaled into v BS by the resistances r B1 and r B2 . In the ideal operation, the maximum value of v B is the amplitude of the input voltage V m . Therefore, the resistances are determined from The input-inductance current i C is sensed by the resistance r I . The voltage across r I is amplified by the current-sense amplifier into v IS with the voltage gain G C . In the ideal operation, namely the pure sinusoid of the input current and the unit PF, the maximum value of i C becomes where R L min is the minimum value of the load resistance. Therefore, r I is determined by: In the transient state, however, there is a possibility that the sensed voltage is higher than V DD . Therefore, the Zener diodes D z1 and D z2 with operating voltage V Z are adopted to the input ports of the DSP to prevent overvoltage, as shown in Figure 1

4.3
Model of FM control Figure 4 shows a block diagram in the DSP controller. In this figure, the variable prime symbol "′" denotes a discrete-time variable. The DSP controller gives the switching frequency f S .

Output-voltage controller
The outer loop derives the reference of input-current amplitude I ′ * ref , which is used for the reference value of the inner control loop. The outer-loop purpose is to regulate the output voltage to V * Or . It is a fundamental characteristic of the class-E 2 DC-DC converter that the output voltage increases as the input current increases. Therefore, the output voltage is regulated by determining the target value of the input-current amplitude I ′ * ref by PI-1 controller, as shown in Figure 1.
The sensing voltage v ′ OS is sampled by every 20 periods of the line voltage. After sampling, the scale is restored by multiplying where m is a natural number. By using v ′ O (m), the input of the PI-1 controller is, The output of the PI-1 controller is the reference value of input inductance current amplitude I ′ * ref (m), which is defined by where K PV and K IV are the proportional and integral gain coefficients of the PI-1 controller, respectively. The transfer function of the output-voltage controller is where  denotes the Z-transform.

Input-current controller
The purpose of the inner-loop control is to shape the input current with unit PF and no harmonic component, as For generating the reference current signal of the inner loop, it is necessary to derive | sin L |, which is realised by sensing the waveform v B because V m is regarded as constant. In the inner loop, the sampling frequency needs to be adjusted to the switching frequency range. Concretely, the switching frequency is updated every 20 switching periods in the proposed converter. Therefore, from v BS , the DSP obtains the reference signal as The input of the PI-2 controller is the error between the reference current i ′ ref and restored input-inductance current, which is The output of the PI-2 controller is the normalised switching frequency ′ (n), which is calculated from where K PC and K IC are proportional and integral gain coefficients of the PI-2 controller, respectively. Namely, the transfer function of the input-current controller is

Control parameter determination
In this work, we can adjust the control parameters K PC , K IC , K PV and K IV based on the developed numerical program. The traditional hand-tuning method for PID controller, Ziegler-Nichols method [40,41], is adopted in this paper. Figure 6 shows the algorithm for tuning the control parameters. Firstly, the current-control parameters K PC and K IC are tuned while the outer-control loop is disabled. After that, the outer-control loop parameters are tuned. These steps are repeated until both control loop shows good stability. In Figure 6, we recognise that oscillation of i C occurs when in the steady state, where Δi * C is the peak-to-peak ripple of i * C during ∕2 < L < ∕2 + 40 ∕ L . Besides, the oscillation of where Δv * O means the peak-to-peak ripple of v * O during 0 < L < 40 .

Problem statement
In the normalised parameters, L , F , C , Q F and Q 0 can be roughly determined. For example, the converter characteristics are almost the same when we elect parameters Q 0 and Q F from the range of 0.1 < Q 0 < 10 and Q F < 0.1. Additionally, C need to be large to ensure the L C works as a choke inductance, for example C > 10. The value of L is sufficiently large because the switching frequency is much higher than the line frequency. Conversely, F should be small, for example, F < 5 for the reduction of the output voltage ripple. Therefore, the major issue of the proposed converter design is to determine the parameters set = [ S , S , D ] for always satisfying the

System design method
The class-E 2 AC-DC converter works in the transient state in the switching-period range. Therefore, it is necessary to establish the design method that can guarantee the ZVS operation in the entire line-voltage period against load variations in the steady-state. In this paper, we propose a novel design method for the class-E 2 AC-DC converter for achieving ZVS against input-voltage variations. Figure 7 shows the flowchart of the proposed design procedure. ZVS achievability of the class-E 2 DC-DC converter against load variations is discussed in [36]. When the converter satisfies the class-E ZVS/ZDS conditions at the nominal load R Lr , the ZVS condition can be maintained at light loads, with the help of FET body diode. However, when the load resistance is smaller than the nominal resistance, the ZVS condition cannot be satisfied. Therefore, for ensuring the ZVS for the whole load-variation range, it is a good strategy to set the smallest load resistance to a nominal resistance, namely L = 1.
Here, we define the DC voltage-transfer ratio of the uncontrolled class-E 2 DC-DC converter as where V O DC is the output voltage of the uncontrolled converter with DC voltage input V I . In the previous researches, the class-E AC-DC converters were designed for M DC = V Or ∕V I . However, in this case, non-ZVS appeared at a certain range of L . Our idea is to consider only M DC as an investigation parameter. When we give M DC , it is possible to determine the parameters Here, V * O ( ) is the average output voltage of one switching period, which is The three conditions in Equation (24) mean ZVS condition, ZDS condition, and rated output-voltage satisfaction, respectively. The converter parameters can be obtained by solving the algebraic equations in Equation (24) numerically with the computation techniques presented in [37,39]. Figure 8 shows the flowchart of the derivation of . Because we investigate just Besides, the ESRs of inductances, normalised forward voltages V * SD and V * F are set to 0. We can determine three parameters from Equation (24) for the given M DC , and the steady-state waveforms of the AC-DC converter are derived numerically from Equation (5). When the anti-parallel diode of the FET is in the on-state at the FET turnon instant, namely, v * S < 0 at S = 2n , it is regarded that the ZVS is achieved. By drawing Figure 9(a), the ZVS region can be comprehended visually. It is seen from Figure 9(a) that non-ZVS occurs in the range of 55 • < L < 90 • when the converter is designed with M DC = 1.9. It is also seen that the ZVS is achieved for the entire line-voltage period if we select M DC in the range of 2.03 < M DC < 2.21. Figure 9(b) shows a contour map of the normalised switching frequency on the L -M DC space. It is seen from this figure that the switching frequency variation range in the line-voltage period is reduced as M DC increases. Because Figure 9 is discussed on the normalised parameter space, this figure is valid for any design specification of the AC-DC converter. From Figure 9(a), we pick M DC = 2.1 for the concrete converterparameter design.

Specifications and circuit components
In this paper, we implemented the class-E 2 AC-DC converter for battery charger applications. The following specifications are given: RMS value of input line voltage V I = 100 V, input line frequency f L = 50 Hz, rated output DC voltage V Or = 190 V, nominal switching frequency f Sn = 1 MHz, and rated output power P Or = 250 W. Output power varies in the range of 0.25 < P O ∕P Or < 1.0. L C = 0.50 mH, L F = 0.84 mH, and C F = 390 F were set in this experiment. From the numerical calculation, the maximum values of the voltages across the FET and the rectifying diode are V SMax = 491 V and V DMax = 550 V, respectively. Therefore, a TPH3208PS GaN-FET from Transform was used as the switch device. From datasheet, we obtain permissible drain-to-source voltage V DSMax = 650 V, on-resistance is r DS = 0.13 Ω, forward voltage of the body diode V SD = 1.6 V, and on-resistance of body diode r SD = 0.14 Ω. Additionally, we used a Rohm SCS302AP SiC Schottky-barrier diode in the class-E rectifier, whose maximum reverse voltage V DMax = 650 V, on-resistance r D ON = 0.2 Ω, and forward voltage V F = 1.35 V. We selected a KBU8D bridge rectifier from Vishay Semiconductor for rectifying the input line voltage, whose on-resistance per diode is r DB = 0.33 Ω.
From the specified Q 0 , R r and f S , we have the resonant inductance L 0 = 17.6 mH. The core material of the resonant inductance was 3F4 from Ferroxcube. The inductance was implemented with two sets of E43/10/28 cores with 0.6 mm air gap. AWG 46 Litz wires with 660 strands were used as the winding wire. The number of turns is N L0 = 6. The measured selfinductance and ESR of the resonant inductance were 18.0 H and r L0 = 0.18 Ω, respectively, at 1 MHz. Similarly, L c and L f were made, whose self-inductance were L C = 0.50 mH and L F = 0.82 mH. The ESRs of L C and L F were r LC = 0.15 Ω and r LF = 0.06 Ω, respectively.
From these component parameters, the three parameters of S , S and D were re-derived from Equation (24) as S = 0.66, S = 0.62 and D = 0.73. By applying the control-coefficient tuning method as shown in Figure 6, we derived the control parameters as K PC = −0.01, K IC = −0.002, K PV = 0.2 and K IV = 1.0. We adopted the TMS320F28379D Delfino DSP from Texas Instruments as the digital controller, whose input withstand voltage V DD = 3.0 V. The input voltage margin of the DSP was chosen as = 0.7. According to Equations (9) and (10), the voltage divider resistances were r B1 = 30 kΩ, r B2 = 470 Ω, r O1 = 30 kΩ, and r O2 = 300 Ω. We adopted a TI INA240A2 current sensor, whose gain is G C = 50. Then, the current-sensing resistance is chosen as r I =0.01 Ω according to Equation (11). Furthermore, for over-voltage protection, we selected two Zener diodes PDZ3.0B from Nexperia as D Z1 and D Z2 , whose operating

FIGURE 10
Photo of the experimental prototype voltage is V Z = 3.0 V. Finally, the Renesas EL7104 low-side gate driver generates the gate voltage v g . Table 1 gives the obtained component values, where all the component values were measured by the Keysight E4990A impedance analyser. Figure 10 shows a photo of the implemented prototype, where the Kikusui PLZ205W electronic load was used as the load device.  Figure 11 shows numerical and experimental waveforms of line-voltage-period domain at the rated load for P O = 250 W, where the experimental waveforms were measured by Tektronix MSO-54 oscilloscope with the TCP0030A current probe. It can be seen that the output voltage is kept at the rated output voltage V Or . It is also seen that the waveforms of input current i I look almost pure sinusoidal. These results showed the validity of the control loops of the proposed FM control system. Figure 12(a) shows PF and THD of the input current as a function of the output power. The THD of the input current is defined as [38] THD = √ ∑ 40

Evaluations of experimental measurements
where I Ik means the RMS value of the kth harmonic current of i I . I I1 means the fundamental frequency component. Besides, PF is defined as where is the phase displacement between the input current i I and input voltage v I . It can be seen from Figure 12(a) that the THD of the input current was in the range from 5.6% to 8.4%, and the PF was larger than 0.995 over the entire load variation range. Figure 12(b) shows harmonic components of i I at the rated output power with the limitation values set by the IEC 61000-3-2 standard limitation. We can see that all harmonic components met the standard. These results verified the validity of the inner loop of the control system.  Figure 13 shows the converter waveforms of the switchingperiod domain at the fixed output power and the fixed linevoltage phase. The input voltages of the converter were almost constant from the view of switching-period domain, but the voltage level varies according to L . In this situation, the output was independent of the line voltage. Additionally, it can be confirmed from Figure 13(a-c) that all the switch-voltage waveforms satisfied the ZVS, which proved the accuracy of the ZVS region in Figure 9(a). Besides, we can see from Figure 13(d-f) that all the switch-voltage waveforms also achieved the ZVS at light load. This result showed the validity of the design strategy that we concentrate on the ZVS achievements at the smallest load resistance. Additionally, we confirmed that the experimental waveforms of both line-voltage-period and switchingperiod domains agreed with the numerical waveforms quantitatively, which showed the effectiveness of the simplified converter model in Equation (5) and the self-development numerical program. Figure 14 shows the waveforms against step load variations. It can be seen from the waveforms that the output voltage converged into the rated output voltage against step load variations. Additionally, the turn-on switching voltage is plotted in Figure 14. Although the hard-switching occurred at the sudden load-change instant, the converter recovered the ZVS immediately. We think these non-ZVS and the switching loss are ignorable. Figure 15 shows the power-conversion efficiency and powerloss breakdown as functions of the output power. Figure 15 shows the power-conversion efficiencies as functions of the output power. For obtaining Figure 15, the power-conversion efficiency is derived by where the input power P I is derived as In the experiments, the input power was obtained from the Tektronix MSO-54 oscilloscope. Besides, the output voltage was measured by the Iwatsu VOAC7523H digital multimeter. Even if the system operated at 1 MHz, the implemented converter achieved high power conversion efficiencies, which was 91.4% at the rated load. This is because the ZVS could be achieved in the entire line-voltage period. It is also seen from Figure 15(a) that we can predict the power-conversion efficiency accurately from the equivalent model in Equation (6). Figure 15(b) shows the power-loss breakdown of the system. In our model, we considered six power-loss factors, namely conduction loss of the FET conduction loss of the bridge rectifier power loss of the input inductance conduction loss of the rectifier diode power loss of the resonant inductance and power loss of the output inductance L F It can be seen from Figure 15(b) that at the heavy load, the power losses were almost proportional to the output power. Therefore, the power-conversion efficiency was almost constant. At the light load, the switch conduction loss P S and resonant inductor P L0 were almost independent of output power, which became the main power-loss component at light load. Table 2 gives the performance comparisons among previous researches on single-switch AC-DC converters. It can be stated from this table that the resonant inductance of the proposed converter is effectively reduced due to the megahertz-frequency operation. The proposed converter can achieve ZVS at all operation points, which can decrease the switching loss despite high-frequency operation. However, the magnetic-component power loss increases compared with the 100-kHz converters due to the AC winding losses and the core losses. As a result, the powerconversion efficiency of the proposed converter was almost the same as the others. This result shows the usefulness of the proposed ZVS-achievement design method. From these comparisons, it can be stated that the proposed converter opens the way to the megahertz operation of the AC-DC converters.

CONCLUSION
This paper presented a single-switch ZVS PFC converter based on the class-E 2 converter at 1 MHz switching frequency. A numerical design method for ensuring the ZVS for the entire line-voltage period was proposed. By visualising the ZVS region in the parameter space, we can easily obtain circuit parameters to achieve the ZVS for the entire line-voltage period. Therefore, the implemented converter achieved the same level of powerconversion efficiency as the 100-kHz-frequency PFC converter. Additionally, we applied a closed-loop controller for achieving a high PF, low THD of the input current, and output voltage regulation. The experimental circuit always achieved the ZVS in the entire line-voltage period against load variations. As a result, the system delivered a high power-conversion efficiency and a high PF with low THD despite the megahertz operation, which denotes the proposed design-method effectiveness. The design of the much higher-frequency AC-DC converter at very-high frequency (VHF) band [31][32][33] and the small-signal analysis of the class-E 2 AC-DC converter are problems we should address in the future.