Ultra high gain step up DC/DC converter based on switched inductor and improved voltage lift technique for high-voltage applications

Voltage lift is a well-known technique to improve the voltage gain of the converter. A combination of switched inductor and the conventional voltage lift technique can be used to achieve high gain, but the semiconductor’s stress is still high. An improved voltage lift technique by employing an extra diode and capacitor and a switched inductor is proposed, which signiﬁcantly increases the voltage boosting factor and reduces the voltage stress of semiconductor devices. The proposed converter is transformerless and non-isolated in nature. The proposed topology has a continuous input source current and has a common connection between the source and the load. The converter is controlled by a single switch, making it simple to use. The steady-state relations are drawn out in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The effect of the unequal inductance on the voltage gain is carried out in detail. The improved voltage lift technique can develop the n- stage converter to improve voltage gain further and reduce stress on semiconductors. The proposed topology is compared with the recent converters, and the effect of the non-idealities on the voltage gain and losses occurring in the components is discussed in detail. A hardware prototype with a rating of 20V/300V, 250 W is built to test the suggested topology’s performance and theoretical analysis. At a 20-V input, the highest efﬁciency was measured to be 95.8%.


INTRODUCTION
Due to greenhouse gas emissions, the globe is experiencing climate change and global warming issues. Compared to fossil fuels, renewable energy sources such as solar photovoltaic (PV), wind energy, and fuel cells are the fastest growing, cheapest and have the least environmental impact. One of the major drawbacks of these sources is the low voltage generated (12-60 V). The use of DC/DC converters to step up voltage (300-400 V) for grid use is required for the implementation of various renewable energy sources. Several battery-powered applications, such as high-intensity discharge (HID) lamp ballasts used in automotive headlights, data centres, and telecommunications systems using 400 V DC buses [1][2], and in railway system a fuel cell battery hybrid tramway use step up dc/dc converters to regulate dc traction bus voltage (700-800 V), require large step up ratios [2].
inductor technology can also be used to increase the voltage gain of the converter by increasing the number of turns in a coupled inductor, but it may cause a voltage spike across the power switch. Furthermore, the problem of leaking inductance losses reduces efficiency. As a result, an additional snubber circuit is required, making the circuit more complicated. In paper [3], a coupled inductor and a switching capacitor are used to achieve high voltage gain. In [4], a three-winding coupled inductor with a voltage multiplier is employed to achieve high voltage gain. The leakage inductance is low because there are fewer turns [4]. Although the non-coupled inductor has a structure similar to that of a standard boost converter, it is related to some boosting approaches and does not have the problem of leaking inductance. One option to enhance the voltage gain of the converter is to cascade the converters, although this reduces the converter's efficiency dramatically. In article [5] a new cascade approach is used to obtain high gain, lower switch voltage stress, and lower conduction losses. Switched inductor [6][7][8][9][10][11], switched capacitor [12][13][14][15], multilevel and interleaved are some of the well-known and accepted approaches. The high voltage is obtained by combining a switched inductor with a switched capacitor cell, as shown in [12], although the converter is only suited for floating loads.
In terms of semiconductor voltage stress and power density, another boosting technology, such as high step-up converters [13][14][15] using switched inductor with capacitor (SC) voltage multiplier, outperforms semiconductor voltage stress and power density. The input source charges the capacitor in the circuit when the switch is on, and the stored energy is discharged when the switch is off, resulting in a greatly increased voltage conversion ratio. The suggested converter in the literature [16][17] does not work across a large duty cycle range. The inductor is substituted by an impedance network in such converters, which are categorized as quasi-z-source or z-source converters. A transformerless active switching inductance (ASL) with a simple structure is shown in [18], along with a low voltage stress on the active switch. Converters are provided in [19] to boost the voltage gain and lower the voltage stress of hybrid switching reactors. As illustrated in [19], an active LC network is implemented to alleviate the ASL network's disadvantage. Two switches are used in these converters, although the converter in [20] does not have a common ground structure. The proposed converter has a common connection between the input source and the output loads. A new impedance network is introduced in [21], and the converter can extend the impedance network in n-stages, but the converter's efficiency suffers as a result.
The step-up converter's continuous input current makes it suited for renewable energy applications. A redesigned SEPIC converter with high gain and constant input current is reported in the paper [22]. Another modified SEPIC structure is presented in [23] by adding four elements. In [24], a buck-boost converter with a continuous input and output port with a higher conversion rate is proposed. Paper [25] presents another buck-boost architecture, although its uses are limited because of a discontinuous input current. A switched inductor voltage multiplier with a capacitor is utilized in a traditional quadratic boost converter (TQBC) in [26] to obtain twofold quadratic gain, but the converter uses three inductors, rather than two as the suggested converter in this manuscript. The voltage stress of the converter shown in [27] is the same as the output voltage, which is a major drawback of the converter.
On the other hand, the converters indicated above only assess the voltage stress on the switch when it is turned off. Furthermore, the voltage stress on power diodes must not be overlooked. Because the voltage stress on the output diodes in the converters outlined above is equivalent to the output voltage, a high-rated power diode should be utilized at the output. In comparison to these converters with minimal voltage stress on the output power diode, the suggested converter has several advantages.
One of the well-known techniques is the voltage lift (VL) technique used to design electronic circuits. The voltage is boosted using a diode and a capacitor across inductors [28][29][30][31][32][33]. Examples of voltage lift techniques are self-lift, re-lift, triplelift, and quadruple-lift boost converters [28]. A similar concept of voltage lift technique is used in [29] across both the inductors of the TQBC. This enhances the voltage gain and reduces the voltage stress on power devices. An active switched inductor LC (ASLC)-based dc/dc converter that uses the voltage lift technique is reported in the literature [30][31], but the converter is suitable for floating loads only. Another converter with the VL technique and the switched inductor is reported in reference [31]. The converter can achieve significantly high gain, but the converter utilizes two switches operated with different duty ratios, making the control circuitry complex, unlike the proposed converter, which uses a single switch. The VL technique is also presented in [32], where the voltage gain is still less than twice of TBC. Similarly, the converter reported in [33][34][35][36] is based on the concept of boosting the input voltage to a very high level; however, the number of components with their voltage and current stress are the main concerns.
An improved voltage lift (iVL) approach is suggested in this literature, combined with a switching inductor network to obtain ultra-high voltage gain. Compared to the conventional voltage lift approach, the improved voltage lift technique needs an additional diode and capacitor, lowering voltage stress on semiconductor devices. In nature, the input current is continuous. Because the proposed topology shares a common connection between the input supply and the load, it is suited for DC Microgrid applications. The technique may be expanded to include n-stages.
The following is how the rest of the manuscript is organized: Section 2 examines the suggested topology's derivation, whereas Section 3 describes the proposed converter's operation and steady-state analysis in CCM and DCM. Section 4 analyses the suggested converter in terms of nonidealities, whereas Sections 5 and 6 give parameter suggestions. In Section 7, the n-stage converter is discussed. In Section 8, the proposed converter is compared. In Section 9, the hardware findings are provided, and the paper is finally concluded.

TOPOLOGICAL DERIVATION
The switched inductor with the capacitor (SIC), as illustrated in Figure 1a, is a common technique for increasing the boost factor or voltage gain by using this impedance configuration in place of an inductor in a conventional boost converter (TBC). Despite the boost factor being double that of TBC, the switch voltage stress matches the output voltage, much like TBC. Figure 1b depicts the use of a voltage-lift cell (VL) in an SIC converter (SIC-VL). In comparison to SIC, the SIC-VL converter has one more diode (D 1 ) and one additional capacitor (C 1 ). This extra energy storage element raises the SIC's voltage gain by (1+k)/(1−k), where k is the gating signal's duty ratio. When the switch is turned on, the input DC voltage source V in charges this additional capacitor (C 1 ). In comparison to SIC, C 1 releases more energy to load. The SIC-VL has a voltage gain of (3−k)/(1−k) when using the conventional voltage lift approach, which is an improvement over the SIC converter. In addition, as compared to SIC, the voltage stress on the switch is minimized. The output diode voltage stress is lower than the output voltage.
An improved voltage-lift cell (iVL) is proposed here, as shown in Figure 1c. Compared to conventional voltage-lift cell, the improved cell is refashioned by utilizing an additional diode (D 2 ) and capacitor (C 2 ) to improve further and reduce the stress of the SIC. A double stage with an improved VL method converter (dSIC-iVL) is presented in Figure 1d to increase the voltage gain further. In addition, compared to the conventional voltage lift approach, the voltage stress on the output diode is lowered even further, and is equal to half of the output voltage detailed later in the literature. Figure 1d shows the suggested configuration of the proposed topology (dSIC-iVL) using iVL cell to obtain the double-stage converter. The configuration consists of a single power switch (S), an SIC impedance network that utilizes two inductors (L Z1 and L Z2 ), two diodes (D Z1 and D Z2 ), and one capacitor (C Z ). The stage 1-improved voltage lift cell in this configuration comprises two diodes (D 1 and D 2 ) and two energy-storing capacitors (C 1 and C 2 ). The stage 2-improved voltage lift cell in this configuration comprises two diodes (D 3 and D 4 ), two energystoring capacitors (C 3 and C 4 ), and D 0 is the output diode. The load is taken purely resistive (R). For the proposed converter's steady-state analysis, the inductance of L Z1 and L Z2 are assumed equal (L Z1 = L Z2 = L Z ). The inductance and capacitance values are sufficiently high so that ripple is negligible. All components are assumed ideal and impedances are linear, timeinvariant, and frequency independent. The steady-state analysis is done in continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

CCM operation of the dSIC-iVL converter with equal inductances
When the converter operates in CCM, the converter operates in two modes. The key waveforms are shown in Figure 2. The equivalent topological circuits in both modes are shown in Figure 3a Applying inductor voltage second balance on inductor L Z1 and L Z2 in steady state for the time interval T S .
From (1), (2), and (3), the capacitor voltages can be found as (4) The relation between the input voltage and output voltage (G CCM ) can be found using Equation (4) The output current (I o ) and input current (I in ) relation is given by (7) The following relationships of voltage stress of power switch (drain to source v DS ) and diodes (cathode to anode) can be derived as The average currents through the inductors L Z1 = L Z2 are I LZ, respectively. The average currents through diode D Z1 , D Z2 , D 1 , D 2 , D 3 , D 4, and D 0 are I DZ1 , I DZ2 , I D1 , I D2 , I D3 , I D4, and I DO, respectively. And the average current through a single switch is I S . The average currents can be derived as

CCM operation of the dSIC-iVL converter with unequal inductances
The operation of the converter depends on converter parameters. The operation of the converter is somewhat different from the case when inductances of L Z1 and L Z2 are equal. Two possible situations are considered Case A: L Z1 > L Z2 and Case B: The current waveform through the inductors L Z1 and L Z2 is shown in Figure 4. The operation of the converter is divided into three modes, as discussed below. inductor currents of L Z1 and L Z2 can be achieved as 2. Mode II: At the start of this mode, the switch is turned OFF. This mode occurs for a short duration of λT S, as shown in Figure 4b. The corresponding circuit diagram is shown in Figure 4b. Diodes D Z1 , D 1 , D 3, and D 0 are forward biased, while diodes D Z2 , D 2, and D 4 are reverse biased. Inductor current I LZ1 is smaller than I LZ2, as shown in Figure 4a. The inductor L 1 charges during this period with a constant positive gradient, and the current L Z2 has a large negative slope and discharge during this mode. The slope of inductor currents of L Z1 and L Z2 can be achieved as 3. Mode III: This mode is the same as Mode II, as in the case of equal inductances. The corresponding circuit diagram is shown in Figure 3b. It can be seen that inductors L Z1 and L Z2 are in series. Diodes D 1 , D 3, and D 0 are forward biased, while diodes D Z1 , D Z2 , D 2, and D 4 are reverse biased. The currents in the inductors L Z1 and L Z2 demagnetize with an equal negative slope which can be achieved as follows: According to voltage second principle balance, the average voltage across the inductor is null. Therefore, On solving (13) and (14) and using voltage relations (1) and (2), it is found that that voltage gain is unaffected as given by relation by Equation (5) From Figure 4a it is clear that the average value of the inductor currents is not equal. It can be noted that the average value of inductor current I LZ2 is greater than I LZ1 .

3.2.2
Case B: if inductance L Z2 is greater than L Z1 Similar to Case A, the operation of the converter is divided into three modes, as discussed below. The current waveform through the inductors L Z1 and L Z2 is shown in Figure 5. The three modes of operation are discussed in this section.

Mode I:
This mode is the same as Mode I, as in the case of equal inductances. The corresponding circuit diagram is the same as Figure 3a. The voltage across the inductors L Z1 and L Z2 is equal to V in . The inductor currents I LZ1 and I LZ2 increase linearly with different gradients. The slope of inductor currents of L Z1 and L Z2 can be achieved as 2. Mode II: At the start of this mode, the switch is turned OFF. This mode occurs for a short duration of λT S, as shown in Figure 5b. The corresponding circuit diagram is shown in Figure 5b. Diodes D Z2 , D 1 , D 3, and D 0 are forward biased, while diodes D Z1 , D 2, and D 4 are reverse biased. Inductor current I LZ2 is smaller than I LZ1, as shown in Figure 5a. The inductor L Z2 charges during this period with a constant positive gradient, and the current L Z1 has a large negative slope and discharge in this period. The slope of inductor currents of L Z1 and L Z2 can be achieved as 3. Mode III: This mode is the same as Mode II, as in the case of equal inductances. The corresponding circuit diagram is shown in Figure 3b. It can be seen that inductors L Z1 and L Z2 are in series. Diodes D 1 , D 3, and D 0 are forward biased, while diodes D Z1 , D Z2 , D 2, and D 4 are reverse biased. The current in the inductors L Z1 and L Z2 demagnetize with an equal negative slope which can be achieved as follows: According to voltage second principle balance, the average of voltage across the inductor is null. Therefore, . dt = 0 (20) On solving (19) and (20) and using voltage relations (1) and (2), it is found that that voltage gain is unaffected as given by relation by Equation (5) From Figure 5a, it is clear that the average value of the inductor currents is not equal. It can be noted that the average value of inductor current I LZ1 is greater than I LZ2 .

DCM operation of the dSIC-iVL converter
The proposed dSIC-iVL converter works in DCM mode the instant inductor currents to zero. There are three different working modes: Mode I, Mode II, and Mode III. The key waveforms are shown in Figure 6a. 1. Mode I: In this mode, the working principle of the converter is the same as Mode I of the CCM operation. The maximum or peak value of the inductor currents through L Z1 and L Z2 can be calculated using Equation (22).
2. Mode II: Power switch S is OFF in this mode. The inductors are demagnetized from peak value to zero at the end of the k 1 T S period. The maximum or peak value of the inductor currents through L Z1 and L Z2 can be calculated using Equation (23).
3. Mode III: The power switch is still OFF in this mode. The energy stored in both the inductor is zero because the current in the inductors is zero. Therefore, the voltage across the inductors is zero. The equivalent circuit is shown in Figure 6b. The energy stored in capacitors C 0 is supplied to the load.
Equating ripple values from (22) and (23), the capacitor voltage C 1 can be found as Also, it can be noted from waveforms from Figure 6 that, in Mode II and using geometry From (27) and (28), the following quadratic can be obtained as is the unified inductor time constant.
The second voltage gain (G DCM ) of the dSIC-iVL converter can be found using relation from (30) (Figure 7)

Boundary mode operation of the dSIC-iVL converter
It is assumed that the proposed converter dSIC-iVL is operated at the boundary of CCM and DCM. The voltage gains of both CCM and DCM are equal. Therefore

PRACTICAL MODEL OF THE dSIC-iVL CONVERTER
In actuality, the converter will have non-idealities that were not considered in the previous analysis. The losses that occur in each component may impact the converter's efficiency. This section calculates the influence of various nonidealities on efficiency and non-ideal voltage gain expression. The inductors' dc resistance is r L , the capacitance's equivalent series resistance is r C , the power switch's ON resistance is r S , the forward voltage drop of the diodes is v D , and the on resistance is r D . Figure 9 depicts the analogous non-ideal model.

Power loss in the switch S
The conduction loss of the power switch (S) is mainly due to the ON resistance of the switch, and root means square (RMS) current through the switch. The current through the switch can be expressed by The conduction loss (P S , conduction ) in the switch can be calculated using Equation (33) as where P o = I o 2 R = 200 W is the output power of the load. The total switching loss (P S , switching ) of the power switch (S) can be expressed as where t r and t f are rising and falling times of the MOSFET during turning ON and OFF. The total loss (P S , total ) in the switch is the sum of conduction and switching loss.
Let r S = 10 mΩ, and (t r + t f ) = 34.71 ns, the total loss in the switches is equal to 3.33 W.

Power loss in the inductors L Z1 and L Z2
The total conduction loss (P L,total ) due to dc resistance of inductor can be obtained as

Power loss in the diodes D Z1, D Z2, and D 0 to D 4
The losses in the diodes depend on current flow and forward voltage drop. The total losses in all diodes are given as The total power loss (P D,total ) is the summation of all the power losses occurring in diodes.
Let v D = 0.4 V and r D = 10 mΩ, the total loss occurring in diodes can be calculated as 7.34 W.

Power loss in the capacitors C Z and C 1 to C 4
The losses occurring in the capacitors depend on the current through the capacitors. The power losses (P C ,total ) of the capacitors due to their equivalent series resistance (ESR) (r CX ) can be obtained as follows: The mean square value of current through capacitors can be found using the following formula (45) The mean square values (I C x rms 2 ) of current through capacitors are expressed in Equation (46) The total power loss in capacitors (P C ,total ) can be calculated as

Efficiency calculation
The efficiency (η) of the dSIC-iVL converter can be expressed as P total,loss is the total loss occurring in the proposed converter and equal to the sum of losses occurring in the switch, inductors, diodes, and capacitors i.e. P total,loss = P S , total + P L,total + P D,total + P C ,total (49) Therefore, the efficiency can be expressed and calculated as

Practical voltage gain
The ideal voltage gain of the proposed converter is derived in (5) as Thus, the practical voltage gain can be expressed as in Equation (52).

PARAMETER DESIGN OF PASSIVE COMPONENTS
The selection of components depends upon the duty cycle (k), switching frequency (f S ), and load resistance (R)

Selection of inductors
The ripple in the inductor currents L Z1 and L Z2 can be obtained during the state when the switch is ON.
Hence the inductance value of L Z1 and L Z2 is calculated using equations where r L1 % and r L2 % is percentage ripple allowed in the inductor currents L Z1 and L Z2 . By considering peak to peak ripple of 1.5 A, the value of inductances can be calculated as So the value of L Z1 and L Z2 can be selected as greater than 0.16 mH.
The following equation in (55) and (56) must be valid to operate the inductors in CCM mode.

Selection of capacitors
The value of capacitors depends on the voltage ripple, duty ratio (k), switching frequency (f S ), and load resistance (R). The capacitors C Z , C 0 to C 4 can be selected by considering peak to peak ripple as 4 V.
where r CZ %, r C 1 %, r C 2 %, r C 3 %, r C 4 %, and r C 0 % is percentage ripple allowed in capacitor voltages. The suitable capacitance value can be selected using Equations (57) to (62). The output capacitor C 0 is selected as 220 μF/450 V, while the rest capacitors are selected as 220 μF/250V.

PARAMETER DESIGN OF SEMICONDUCTOR DEVICES
Power switch and diode parameter selection is based on their current and voltage stresses, reported in Table 1 and estimated in Section 3.
For the prototype of rating 20 V/300 V, voltage rating must be greater than 100 V and current ratings greater than the input current. C3M0065090J Silicon Carbide Power MOSFET is selected with blocking voltage of 900 V and STTH30R04, ultra-fast recovery diodes are selected with blocking voltage up to 900 V.

PROPOSED n-STAGE CONVERTER (nSIC-iVL) CONVERTER
The double-stage converter dSIC-iVL can be extended into nstages. The nSIC-iVL converter has a single switch S two inductors, L Z1 and L Z2 . The converter has a single input source V in and a single load. The total number of capacitors in the n-stage structure equals (2n+2) and the total number of diodes is (2n+3). The circuit diagram is shown in Figure 10 Based on the analysis in Section 3, the voltage gain (G n−CCM ) in CCM of the n-stage proposed nSIC-iVL converter can be expressed as The voltage gain (G n−CCM ) of the n-stage proposed converter is depicted in Figure 11 for different stages and duty ratios.
The capacitor voltages of the n-stage proposed nSIC-iVL converter can be expressed as The capacitor voltage of the n-stage proposed converter (nSIC-iVL) is depicted in Figures 12 and 13 for different stages and duty ratios.

FIGURE 13
Even capacitor voltages of n-stage converter (nSIC-iVL) The voltage stress on the switch (drain to source v DS ) and diodes (cathode to anode) can be expressed as The normalized stress on semiconductors (diodes and switches) is shown in Figure 14. The voltage stress on the semiconductor devices reduces as the number of stages increases. The average input current (I in ) can be expressed as The average inductor currents of inductors L Z1 and L Z2 can be expressed as The average currents through diodes can be expressed as The average current through switch (S) can be expressed as

COMPARISON WITH THE SIMILAR DC/DC CONVERTER
We compare the suggested converter to current topologies that have been employed in the past in this section. When evaluating converters, voltage gain, voltage stress on semiconductor devices, total device rating (TDR), common ground, and input current type are all taken into account. Figure 15 shows a comparison of the proposed converter's boosting capabilities. In all duty ratio ranges, the suggested converter with n = 3 has the maximum voltage gain of all the stated converters in Table 2. The suggested two-stage converter (n = 2) has the maximum TABLE 2 Comparison with the similar DC/DC converters gain until k = 0.5, after which converter G has the highest gain owing to quadratic gain; however, the converter G has several drawbacks that will be detailed later in this section Furthermore, the suggested converter incorporates an expandability feature that further boosts the voltage gain. A single switch is used in the dSIC-iVL converter, whereas two switches are used in converters A, B, C, D, E, F, and H. Two inductors equal to TQBC are used in the proposed dSIC-iVL converter, converters A, B, C, G, and H. Converters E, I, and J use three inductors, converter F has four inductors, and converter D has the most inductors; however, the dSIC-iVL converter has the maximum voltage gain. The suggested dSIC-iVL converter has the largest number of capacitors. Seven diodes make up the dSIC-iVL converter, which is the same as the converter F. The maximum number of diodes in the converter D is eight. The total number of components is highest in converter D, whereas the proposed dSIC-iVL converter and converter F have 16 components.
Attributed to the reason that voltage gain is not a sufficient criterion for evaluating the converter's performance, different devices were used to compare the converter. Figures 15 through  19 show the voltage gains per inductor count, switch count, diode count, and capacitor count. Other converters have the lowest voltage gain per inductor count and switch count. However, when the number of stages increases, the voltage gain per inductor and switch rises because only diodes and capacitors grow in number, while inductors and switches remain constant, as shown in Figures 16 and 17. The proposed converter has voltage gain per capacitor count equal to converter A, TBC, and C, as shown in Figure 18. The voltage gain per diode count is shown in Figure 19. It can be seen from the same figure that voltage gain per diode count is greater than converters B, D, I, and F.
The switch's voltage stress is critical for assessing DC/DC topologies. Figure 20 provides a graphical representation of the switch's normalized voltage stress. Of all the reported converters included in the comparison (Table 2), the suggested  Figure 20. In Figure 21, the maximum voltage stress on the diodes is also compared. In general, like the TBC, TQBC, converters A, B, C, and F, the output diode has voltage stress equal to the output voltage. The suggested converter eliminates this drawback. Among all the converters studied, the voltage stress on the diodes is the lowest. The normalized diode voltage stresses in the proposed converter decrease as the number of stages rises, as shown in Figure 21. Low voltage stress on semiconductor components reduces costs while increasing efficiency. The sum of the individual product of current and voltage ratings is the TDR. Table 2 shows how the TDR of all converters at 200 W is determined given the exact operational requirements. The proposed converter has a lower TDR rating except for J, H, and E converters.
Unlike converters B, D, F, and I, the converter has a common connection between input and output, making it ideal for a broad range of applications. Furthermore, there is no extra dv/dt between the input and output grounds. The converter is suited for MPPT applications because it has a continuous input current. As a result, it can be stated that the suggested converter outperforms the other converters in terms of voltage gain, voltage stress on semiconductor devices, total device rating, common ground connection between source and load, and converter expandability. EXPERIMENTAL RESULTS

DISCUSSION IN CCM MODE
This subsection determines the actual world performance evaluation of the double-stage dSIC-iVL converter. Figure 22a shows the hardware prototype, with specifications listed in Table 3. PWM gate signals are generated by an FPGA Vertix-5

FIGURE 23
Top to bottom: experimental waveforms of input supply voltage, input current, output voltage, and output load current at duty ratio equal to 0.6 (XC5VLX50T) controller to control the power switches externally. In addition, as illustrated in Figure 22b, a driver circuit GDX-4A22S1 is used to increase the gate signal to the requisite level to trigger the MOSFETS. The block diagram of the proposed converter and the block diagram of the control technique to generate the gate pulse are shown in Figures 22b and 22c, respectively. A MUX, comparator, logic gate, constant, and counter block are used to create the switching pulses. To create the PWM pulse for the switch (S), a counter block generates the carrier waveform (sawtooth) and compares it to the output of MUX.
The input supply is set to 20 V, and MOSFET is controlled with a gate pulse of 60%, as shown in Figure 23. The steadystate output voltage (V o ), load current (I o ), and input current (I i ) are captured in the same figure and are equal to 299 V, 0.74 A, and the continuous input current is observed with a load resistance of 400 Ω. The dip in the V o from the ideal value is due to the non-ideal behaviour of the components. However, the input current is pulsating in nature with high ripple content. The converter can achieve a boosting factor of 14.95 under these circumstances. With a fixed duty ratio of 60% and a load resistance of 400 Ω, the switch voltage (V ds ), currents of inductor L 1 (I L1 ) and L 2 (I L2 ) waveform are captured in Figure 24. In the same figure, the inductor currents I L1 and I L2 rise when the switch voltage across the switch is near zero. The inductor's currents rise from 4.5 A to a peak value of 6 A. When the switch is OFF, it blocks a voltage of 100 V, which is precisely one-third of the output voltage (V O = 299 V). The inductor currents decrease from the peak value of 6 A to an initial value of 4.5 A. The average inductor current is observed equally to 5.62 A. The percentage of inductor current ripple observed is 22%.
The diodes D 2 , D 4, and D Z1 are reverse biased when the switch is OFF, as shown in Figure 25. The peak reverse-biased voltage of D 2 and D 4 is observed near 100 V, which is approximately 33% of the output voltage. In Figure 26, the reversebiased voltage of diode D Z1 is 50 V. When the switch is ON, the output diode D 0 is reversed biased, the peak voltage of the output diode is 100 V, one-third of the output voltage, and the capacitor C 4 voltage is 100 V.
When the duty ratio (k) is changed from 60% to 70%, with a fixed input supply of 20 V and load resistance, the output volt-

FIGURE 27
Top to bottom: experimental waveforms of input supply voltage, input current, output voltage, and output load current at duty ratio equal to 0.7 age increases to 398 V, as captured in Figure 27; it can also be observed that there is an increase in the load current near 1 A. The input current is also increased but is continuous in nature. The converter performance is also examined in dynamic conditions by changing the duty ratio at different levels with a constant load resistance of 400 Ω and maintaining input supply at 20 V. The step change in the duty ratio from 50% to 60% increases the output voltage from 240 to 299 V. The output load current is changed correspondingly from 0.6 to 0.75 A. The input current also increases, as seen from Figure 28. The duty ratio decreases to 0.4; the output voltage decreases to 200 V, the load current decreases to 0.5 A, and the input current decreases. Further, the duty ratio is increased to 70%, the output voltage is increased to 398 V, the load current is increased to 1 A, and the input current is increased (Figures 29, 30, and 31) The actual voltage gain is represented in Fig. 29. The deviation is seen since the real model of the converter will have parasitic resistance in inductors, diodes, switches and capacitors and forward voltage drop in the power diodes. The percentage experimental efficiency of the converter is plotted in Fig. 30 at different output power levels. As the output power is increased

FIGURE 29
Ideal and experimental voltage gain the efficiency first increased and reaches a maximum value near 96% and then decreases at higher output power levels. The converter efficiency at 200W output power is 92%. The loss distribution among the components is shown in Fig. 31. The maximum loss is occurring in the diodes equal to 40% of the total loss i.e. 18.62W. The percentage of loss in the inductors is 30%, switch loss is 18% and losses occurring in the capacitors is equal to 12%.

CONCLUSION
The proposed converter originated using switched inductor and improved voltage lift technique. The converter has fixed two inductors and a single switch. The converter has a number of benefits, including ultra-high voltage gain, low-voltage stress on switches and diodes, including the output diode, continuous input current, common ground connection between source and load, and the ability to expand into n-stages (nSIC-iVL) with fixed two inductors and a single power switch. The control is simple at all levels thanks to the single switch. When the converter stages are raised, the output voltage acquired forms a series in an increasing arithmetic progression. In addition, as the number of stages increases, the voltage stress on semiconductors decreases. The steady-state analysis was investigated in CCM, DCM, and boundary condition mode. Non-ideal analysis, component power loss, efficiency, and non-ideal voltage were all examined. The proposed converter was compared with recent DC/DC converters; the voltage gain per inductor count, diode count, and switch count was significantly high. The switch voltage stress and diode voltage stress are lower than recent converters. The total device rating was lower than the recent converters. The input current was pulsating in nature with high ripple content, which sets a limitation to the proposed converter. A 250 W hardware prototype was tested for various power ratings, and the highest efficiency was discovered to be 95.8%. The converter's performance under dynamic conditions was found to be satisfactory, and experimental findings were found to be in good accordance with theoretical results. The converter is transformerless and belongs to the non-isolated group. As a result, the converter is a good fit for high-voltage applications.

ACKNOWLEDGEMENT
This publication was made possible by NPRP grant # [13S-0108-20008] from the Qatar National Research Fund (a member of the Qatar Foundation). The statements made herein are solely the responsibility of the authors. The APC for this paper is funded by the Qatar National Library, Qatar.

FUNDING INFORMATION
Funding Agency: Qatar National Research Fund (a member of Qatar Foundation), Funding No. NPRP 13S-0108-20008