Transient current effect on the dye sensitized solar cells
 I
 –
 V
 characterization

Correspondence Rached Gharbi, Ecole Nationale Supérieure d’Ingénieurs de Tunis, Laboratoire d’Ingénierie des Systèmes Industriels et des Energies Renouvelables, Université de Tunis, 05 Av. Taha Hussein, Montfleury, Tunis 1008, Tunisia. Email: rached.gharbi@ensit.rnu.tn Abstract A choosing process for the sampling delay in the dye sensitized solar cells I–V characterization method was established. The presented method is based on the stepwise varying bias voltage technique. The analyses were based on the solar cell transient current impact on the cell I–V acquisition. This process presents a method to correctly fix the I–V scan sampling delay concerning the cell settling time to obtain accurate dye sensitized solar cells performance measures. It allows a faster acquisition compared to classical measurement method to avoid the solar cell heating. All tests were performed on a typical TiO2 natural-dyed solar cell, dedicated to laboratory tests. The cell manufacturing process was also discussed. Measures were operated by a laboratory developed digital acquisition board. The system architecture, as well as its operating algorithm, was presented.


INTRODUCTION
The dye-sensitized solar cells (DSSCs) are one of the promising photovoltaic (PV) devices nowadays [1]. This is due to their simple low-cost production process, their composition flexibility and their clean manufacturing techniques comparing to the conventional Silicon (Si) cells [2][3][4][5]. Subsequent to about three decades, researches still incessantly strive to increase the DSSCs efficiency by enhancing its manufacturing process and constituting materials. Hence, these PV devices exist in a very large number of morphologies with several built-up procedures and various assembling materials.
To accurately evaluate the different reported cells occurrences, a unified process for DSSCs current versus voltage (I-V) characterization and performance measures is required. The most used characterization process is built on previous researches and standards [6,7]. Its approach is to setup and apply a stepwise (ΔV) varying bias voltage supply on the solar cell (SC) to obtain its I-V characteristics as shown in Figure 1. Where the scan sampling delay (T d ) should be more than four times as long as the cell settling time (τ) [7]. Usually, a DSSC characteristic capacitance can achieve tenths to tens of mF/cm² [8][9][10][11]. Accordingly, the I-V characterization sampling time must be about one to ten seconds, depending on the DSSC morphology, This article comes to present an investigation on the DSSC capacitive behaviour and its transient output current. The results are used to implement a practical method that performs accurate DSSC I-V measurements.

Solar cell preparation
A typical natural DSSC has been made for all this work experiments [12][13][14][15]. The cell electrodes are a Fluorine doped Tin Oxide (FTO) Glass Substrates. Their dimensions are 25 mm × 25 mm × 2.2 mm each with an approximately 7 Ω/cm 2 of conductive surface resistivity. 2 g of nanocrystalline titanium dioxide (TiO 2 ) nanoparticles powder (P25), purchased from Degussa Chemicals (Hanau, Germany), are used to prepare the cell Ntype thin film. The TiO 2 particles are sized of 21 nm and an 80% / 20% anatase / rutile composition. The powder was mixed with 2.5 mL of absolute ethanol solution (>99.5%). Three drops FIGURE 1 I-V measurement scanning wave considering DSSC high characteristic capacitance. Where "τ" is the cell settling time. "T m " is the measurement time. "T d " is the scan sampling delay. "T hold " is the holding time that considers the setup delay of the system after the solar cell installation The titanium dioxide paste arrangement on the SC electrode using the doctor blade technique, (b) The final sealed DSSC where the two electrodes were fit together using binder clips of diluted acetic acid (3 × 1/20 mL), developed by 0.1 mL of its glacial solution mingled in 50 mL of distilled water, were added to the mixture [16,17]. The mixture was slowly grinded for 20 min to obtain a colloidal paste without air bubbles. The obtained suspension was extruded and arranged on the anode conductive-surface using the doctor blade technique [18,19]. The final film dimensions are 1.1 cm x 1.1 cm. The all set substrate is presented on Figure 2(a). It has occurred a Rapid Thermal Processing (RTP) at 500 • C to obtain an anatase/rutile settled mixture [20,21]. The counter-electrode is a typical FTO substrate covered with a thin carbon layer by fumigation process [22][23][24]. The cell dye is a natural juice extracted from the blackberry fruit. The fruitlets have been crashed and mixed with 250 mL Anode substrate was dipped in the mixture to acquire the blackberry color as shown in Figure 2(b) [25][26][27].
The encapsulated electrolyte, shown in Figure 3, is a few drops of volatile iodide/tri-iodide redox couple solution (Triiodide). The inhouse thickness was maintaining by using two hollow Surlyn tapes (2 × 0.254 mm). This fixes the cells geometric properties regarding the characteristic capacitance along the different manipulations. A shading mask, with 1 cm² of aperture area (A) was used to set up the cell active area.
DSSCs are known by their high characteristic capacitance. This specification comes from the existence of two charged layers (Helmholtz Layers) in the cell composition as shown in the Figure 3. The use of nanoparticles, such as the TiO 2 , increases the internal surface of the porous electrode from 100 to 1000× greater than the geometric area of the electrode. Hence the surface capacitance of the TiO 2 interface / Dye / electrolyte in the cell becomes of the order of mF/cm². This flaw increases the DSSC settling time, and causes noticeable transient current once the cell is scanned with ΔV varying bias voltage supply [8].

Test bench
The test bench is presented in the Figure 4(a). The DSSC measures including the I-V characteristics, transient output current and substrate temperature were performed using a laboratory developed digital acquisition board (DAQ) illustrated in Figure 4(b). The system is developed to be suitable for DSSC measuring process. The design is based on a Cortex M4 Microcontroller Unit (MCU) that includes a digital to analog converter (DAC) to generate the scan waves. The two functions f 1 (v) and its reverse f 2 (v) level-adjust voltages on the force and measurement lines between the MCU DAC and analog to digital converter (ADC) and the SC terminals. They are based on a rapid rail-to-rail junction field effect transistor (JFET) operational amplifiers (OpA) network. The function f 3 (i) is based on a high slew rate (17 V/μs) JFET OpA network to adapt the sensing current to the MCU ADC measuring voltage.
The system is connected to the SC with kelvin clips. The test leads presented in the Figure 4(b) are Forcing/Sensing couple terminals termed HI F /HI S , for the cell positive side (HI), and The acquisition board architecture. Were "τ" and "θ" sensing wires represent the cell settling time and temperature signals. "V off " and "V(I off )" are two potentiometers that allow offset adjustment while the circuit calibration LO F /LO S for the negative one (LO). Both the DSSC temperature and "τ" are measured via two additional test probes presented as θ/τ sensing line. The low current to voltage converter μL/U is a part of the forcing lead HI F to ensure the acquisition accuracy.
The system allows a nearby 20 μV / 0.5 nA of voltage/current scanning resolution. A universal asynchronous receiver transmitter (UART) to universal serial bus (USB) connection is set to connect the board to a personal computer (PC). All the processing is executed upon a supervision graphic user interface (GUI). Besides the DAQ, the test bench covers a PC The characterization process was performed using a lab calibrated lighting source with 100 mW/cm² power density. Its irradiance spectrum is given in Figure 5.
The microscopically DSSC observations and measures were taken using an ultra-nano-indenter CSM Instruments optical microscope.
To complete the cell examination, the X-ray diffraction (XRD) pattern of the used sample was recorded, and the test was carried out by means of the Malvern Panalytical diffractometer Empyrean. Figure 6 shows the system software flow chart. The manipulation routine can be described as follows. After starting the system, the DAQ remains in hold until the DSSC installation in the testbed. Next, the process starts by measuring the SC parameters: Open circuit voltage (V OC ) and short circuit current (I SC ). During all the measurements, the system acquires the cell temperature variation (Δθ) for featured corrections. Thereafter, the system determines the DSSC settling time by performing a quick transient testing scan, around the "V OC " point.
After fixing "τ", the manipulator is called to choose the scanning parameters referring to the obtained results on the GUI. These preferred factors, also presented on Figure 1, are the scan sampling delay "T d ", the voltage changing level "∆V", the scan direction and the holding time "t hold " between scans. The system validates the selected parameters if the total measuring time does not exceed 1 min. Afterward, the I-V characterization could be launched, and all results are stored, analysed and displayed within the GUI.

The DSSC electrode verification
The DSSC thin film XRD (X-ray Diffraction) patterns are given in Figure 7. The characteristics shows the crystalline peaks of both anatase and rutile TiO 2 structure in the 500 • C annealed

3.2
The DSSC I-V characterization results and discussions Figure 9 was acquired using the digital oscilloscope. It presents the DSSC transient current wave around the V OC point in a  Previous researches show that using the average values of the both sweep direction could strongly minimize the total scan time [8]. The main manipulation in this work consists in making I-V sweepings in both directions, direct and reverse. Every sweeping was made with a defined speed, related to the DSSC settling time, to obtain the point from where the tests can be considered as accurate.
A noticeable dependence between the measures and the scan sampling delay and sweeping direction is obviously shown in the curves.
The measured cell performances are presented in Table 1. Results are given for both scan directions: Direct (D) and Reverse (R). The SC short circuit current-density (J SC ) and efficiency (η) values are calculated using the Equations (1) and (2) [17,28].
Where "I SC " is the DSSC Short Circuit Current in "mA" and "A" is the cell active area in "cm²" [29].
Where "P max " is the DSSC maximum recorded power value in "mW" and "E tot " is fixed by the lighting source at 100 mW/cm². The results show the DSSC under test response versus the "T d " changes. The cell "V OC " value in the direct sweep

FIGURE 11
Average efficiencies and related relative errors versus the sampling time variation has fallen from 0.513 to 0.501 V meeting the "T d " decrease. Inversely, "V OC " has increased from 0.515 to 0.546 V in the reverse scan. Also, the DSSC short-current density "J SC " value has decreased in direct scan from 0.878 to 0.865 mA/cm² and increased in the reverse scan from 0.879 to 0.910 mA/cm². The DSSC efficiency relative error (ε r ) is calculated using the Equation (3), where the cell efficiency (η) at "4.τ" is considered as the accurate "η" value. "η avrg " is the direct and reverse efficiencies average calculated using the Equation (4) and its relative error is extracted from the Equation (5) [30].
Unlike in the new proposed approach, η avrg and ε avrg are not calculated for the classical method because it does not use averaging between direct and reverse scanning values. It takes only one scan direction into consideration [7].
Observing the DSSC performances, the cell efficiency has changed dramatically vis-à-vis the scan speed variation. Results show an efficiency decrease in the direct scan from 0.30%, which is considered as the accurate value, to 0.17% when "T d " vary from "4.τ" to " 1 10 .ø" value. Differently, "η" has increased from 0.30% to 0.67% in reverse scan. It is important to mention that the reverse measures presented at 5 ms are estimated; otherwise, the last value of real measure in reverse sweeping is η = 0.50 %, which is taken for 10 ms as sampling delay. Figure 11 shows the variation of the cell efficiency after averaging the both directions values for each T d value. It shows also the related relative error regarding the considered correct effi-ciency η = 0.30 %. Results shows that measures are considered highly faulty if the sampling delay is shorter than "1.τ", which gives 1.7 % of relative error. Hence, choosing a "T d " value over "1.τ" rate (50 ms) gives accurate performances results after averaging the two sweeps measures.
As it was mentioned in the introduction. The classic I-V characterization sampling delay must be about one to ten seconds. Although, increasing the sampling delay increase the DSSC temperature variation as shown in Table 1. The temperature variation of the dye solar cell in the classical method has reached +15.3 • C. The Standard Testing Conditions (STC) necessitate that measurement must be done under ±1 • C of cell temperature variation (Δθ). Getting much deviation make the I-V characteristics susceptible to many errors and further corrections are needed [31][32][33]. Also, the classical method results for cell performances present a high relative error, 10% in direct scan mode and 6.7% in the reverse one. These values are relatively high comparing to the new method results which use a fast scan averaging procedure.
Considering the obtained results, the eventual measurement sampling delay is "1.τ" because it gives a reasonably temperature variation Δθ = +1.6 • C and its measures relative error after averaging is relatively low (1.7%). Increasing "T d " more than "1.τ" risks to heat the cell more than +2 • C which is wide out of the STC requirement. Due to the numerous morphologies of this SCs, researches show that the DSSC dependence regarding the temperature variation is bound to the materials and the used techniques for its manufacturing [33][34][35][36]. However, our approach of "T d " value choice remains valid, slightly exceeding beyond the "1.τ" value is desirable only if the DSSC did not undergo a temperature variation remarkably superior to |Δθ| = +1 • C. Otherwise, a data correction must be applied to the measures. This process guarantees that the calculated performances translate correctly the real case of the cell [33].

CONCLUSION
This study presented a practical and generic solution to perform accurate electrical characterization for DSSC with high characteristic capacitance. The analyses were based on the scan sampling delay impact on the cell I-V acquisition. The examination has shown that the influence of the cell capacitance on the performances measures can be overcome if the results are given by averaging a double direction sweep measures. This hypothesis was effective with 1.7% of performance measuring accuracy if the sampling delay is equal to the cell settling time. Measures can be considered more accurate if the sampling delay passes this minimal value once the cell temperature variation does not get more than +1 • C. Otherwise, a data correction will be needed. Unlike the classic method where the sampling delay is over one second, this method allows faster scan to avoid the solar cell heating. However, the conventional method gave an error of 6.70% at least and 15.3 • C of cell total heating. When the proposed process was more accurate with only +1.6 • C of cell temperature rise.