Ultra‐low power TIA with variable bandwidth in 0.13 μm CMOS for short‐range optical interconnects

Funding information Nazarbayev University (NU) Faculty-Development Competitive Research Grant, Grant/Award Number: 021220FD0451; NU Collaborative Research Grant, Grant/Award Number: 021220CRP0422; Ministry of Education and Science of the Republic of Kazakhstan, Grant/Award Number: AP08856931 Abstract An ultra-low power and variable bandwidth transimpedance amplifier (TIA) for shortrange optical interconnects is presented here. The TIA is implemented in a 0.13μm complementary metal oxide semiconductor (CMOS) technology. To reduce the power consumption, the TIA is designed using a regulated cascade topology with capacitor degeneration for frequency enhancement and also operates in the weak inversion mode. With a supply voltage of the range 0.7–0.92 V, a reduced power consumption of 2.9–4.6 mW and a variable bandwidth of the range 3–4.9 GHz are achieved. Clear eye diagrams are obtained at 2.5–6.135 Gbps and a BER of less than 10−12 with input power of −4.3 to −3 dBm at 2.5–6.135 Gbps, respectively. Also, the TIA achieved a transimpedance gain of 51.2–52.4 dBΩ. The small-sized chip occupied an area of 0.28 × 0.42 mm2 with pads and 0.1 × 0.1 mm2 without pads.


INTRODUCTION
Optical interconnection technology is one of the potential and preferred technologies for meeting with the current trend of increasing the density of interconnection and reducing power consumption for the next-generation and high-performance computing systems, when compared to electrical interconnects. Optical interconnects exhibit several advantages over their electrical counterparts such as lower inter-channel crosstalk, higher bandwidth, and lower power consumption [1][2][3][4]. With power playing a significant role in determining system cost, the use of dynamic power management techniques is becoming increasingly common [5,6]. There have been a number of reports that detail techniques to improve the I/O power efficiency in analog circuits and mixed signal circuits [7][8][9][10][11][12], and also in electrical interconnects [4,5]. For example, device-level scaling is one of the low-voltage circuit techniques. However, one of the issues with this method is increased threshold variation. Threshold variation depends on both device and process parameters such as channel length and width, oxide thickness, junction depth, and substrate doping concentration. Other low-voltage circuit techniques include bulk-driven, floating gate techniques, flipped voltage follower technique, and bulk-driven flipped voltage follower technique. A scalable transceiver was reported with the power efficiency of 2.8-6.5 mW/Gbps by using scalable transceiver circuit blocks and joint optimization of supply voltage, bias currents, and driver power with data rate [13]. Similarly, it has been demonstrated that low swing voltage mode drivers significantly reduce driver power [14,15].
Over a period of time, it has been proven that the use of optical interconnects have a number of benefits over their electrical counterparts [16]. While this is true, there have been reports of numerous research articles that deal with the minimization of power consumption in optical interconnects. Essentially, to reduce optical link power consumption, each component of the link should optimize the power efficiency. The transimpedance amplifier (TIA) is one of the important circuits of optical interconnects and extensive research has been pursued towards reducing the power consumption of the TIA in the past decade [17][18][19]. An optical receiver is made up of TIA, limiting amplifier/gain stages and output buffer. Thus, the TIA is a very important part of an optical receiver. A 2.2 mW TIA was designed in 80 nm complementary metal oxide semiconductor (CMOS) technology with a trade-off of higher input-referred noise to achieve high speed and low power consumption [17]. Another work on an ultra-low power receiver achieved low power consumption by employing complicated design of RC double sampling front end and a dynamic offset modulation technique in a 65 nm CMOS technology [18]. However, these two designs although very interesting, are based on scaled technologies which are expensive and have complex circuit topology. To address this aspect, the regulated cascade (RGC) topology with capacitive degeneration and resistive feedback were employed to achieve low power and high bandwidth [19]. Although this design employs the RGC topology and capacitive degeneration, the resistive feedback and the extra buffer stage not only adds to the complexity but also affects its power consumption and total size. Overall, these circuits do not support operation for a wide range of supply voltage and the bandwidth may severely degrade at lower voltages and hence can be inoperable even at lower bit rate.
To address the above concern, a scalable supply voltage and frequency TIA with an active-load inductor to boost the bandwidth was introduced [20]. However, the active-load inductor in such a design might lead to flatness of the frequency response and hence can make the performance of the TIA at high frequency degraded. In addition, the noise and input sensitivity of the TIA, which are very important parameters in determining its performance, were also not reported in the paper. Furthermore, the use of variable resistors for different voltage levels complicates this architecture. Subsequently, a current controlling PMOS array and a tuneable resistive bank is implemented to optimize the power consumption and bandwidth but at the cost of increased complexity in the architecture [21]. There have been reports of transistors working in weak inversion region for ultra-low power consumption [7,22]. In this region, there are some advantages including high voltage gain, less distortion, and ease of compensation with degradation in the noise margin.
Here, a simple TIA using RGC input and capacitive degeneration in the gain stage with the transistors working in weak or moderate inversion mode has been explored for ultra-low power consumption in 130 nm CMOS technology. The TIA operates in the weak or moderate inversion mode and as a result, the bandwidth of the TIA is reduced due to the lowering of the cut-off frequency of the transistor in such modes. However, in these modes, the voltage gain of the transistor increases, and the bandwidth improves due to the capacitive degeneration. Also, due to operation in the weak or moderate inversion mode, low power consumption is achieved. A comparison table and discussion demonstrates the effectiveness of the proposed topology. Though the circuit allows for variable bandwidth operation, if designed in lower technology node, has the potential to provide a number of benefits associated with lower technology nodes. Section 2 provides extensive description of the proposed circuit and the corresponding analysis. Section 3 is dedicated to measurements and discussion while the Section 4 concludes this paper.

RGC Input
Cap Degenerator Small-signal circuit model of (a) the RGC and (b) the output stage of the proposed TIA

CIRCUIT DESIGN AND ANALYSIS
The schematic of the proposed TIA employing RGC topology is shown in Figure 1. The RGC topology reduces the input impedance by the amount of its own voltage gain. The RGC topology reduces the capacitive effect of the photodiode (PD) and also prevents the input pole from dominating the bandwidth of the entire TIA. Figure 2 shows the small-signal circuit model of the proposed TIA. The input impedance of the RGC input is given as: where 1 + gm 2 R 2 is the gain of the local feedback. Thus, the amount of reduction of the input parasitic effect is determined by the size of the local feedback. A transistor biased in the weak inversion region maintaining approximate relation between the drain current, gate-tosource voltage V gs and drain-to-source voltage V ds is given by expression (2) [22]. Here, n and I D0 can be extracted from experimental data, k is Boltzmann's constant, T is the absolute temperature, and n is the channel-noise factor of MOSFET.
The value of n ranges from approximately 1.6 in weak inversion to 1.3 in strong inversion for an nMOS device [23]. The transconductance can be deduced by differentiating Equation (2) with respect to V gs as expressed in Equation (3). It is apparent that the drain current directly affects the transconductance in the weak inversion region.
Subsequently, the transimpedance of the TIA can be expressed by Equation (4). In this expression, gm 1 , gm 2 , and gm 3 are the transconductances of M 1 , M 2 , and M 3 , respectively.
Furthermore, C eq1 = C pd + C gs1 + C sb1 ; C eq2 = C gs1 + C gd 2 ; In the above, r ds1, 2, 3 is the drain-source resistance which is the small-signal output impedance r o ≈ (1/λI d ), which is inversely proportional to λ, the channel length modulation factor. It can be inferred from Equation (4) that the TIA has two zeros and three poles; in particular, it has a zero at −(1/R 4 C s ) and a pole at −(1 + gm 3 R 4 )/R 4 C s from the degeneration stage. With the appropriate value of R 4 , C s and g m3 , the zero from the gain stage can be used for compensating the dominant pole of the TIA and the 3-dB frequency is determined by the secondlowest pole of the circuit 1/(R 2 (C eq3 + C eq2 )). However, the capacitor degeneration works as a filter for the gain stage to enhance noise performance of the TIA. Further, the degeneration capacitor value should be carefully chosen so as to improve bandwidth performance. An optimal value of 450 fF was used as C s . Now the low frequency gain of the TIA can be expressed by Equation (5). .
The term K 3 in Equation (6) is expressed in Equation (7).
In Equation (6), because r ds3 > > R 3 and r ds3 > > R 4 , when the I D changes in the weak region, a small change in r ds3 does not have much effect on the low frequency gain of the TIA. This is also clear from the small/negligible change of transimpedance gain at low frequency in the frequency response plot in Figure 3. Figures 4 and 5 show the relationship between bandwidth with supply voltage and transimpedance gain with supply voltage of the proposed TIA under moderated and weak inver- The sensitivity is another important parameter for a TIA and it is dependent on the input-referred noise of the TIA. The input-referred noise of the proposed TIA is given by Equation (8). Here, k is the Boltzmann's constant, T is the absolute temperature, and Γ is the channel-noise factor of MOSFET. I n,eq ≅ 4kT It can be observed in Equation (8) that the low frequency noise is dominated by thermal noises whereas the high frequency noise worsens as the input parasitic capacitances increase. The simulation results of the input-referred noise of the TIA with different supply voltages is given in Figure 6. Apparently, as the supply voltage increase, the noise of the  TIA degrades at low frequency but improves at 3-dB frequency. However, the 3-dB frequency can be further increased at higher supply voltages in the absence of high noise. In brief, high noise constitutes one of the trade-offs of operation in weak inversion mode.

MEASUREMENT AND DISCUSSION
The TIA was designed and fabricated in a 0.13 μm CMOS technology with six metal layers. The Figure 7 depicts the photographs of TIA chip and its packaging. Including the ESD pads, the TIA chip occupies a total area of 0.42 mm × 0.28 mm. The TIA was die bonded to an evaluation printed circuit board and wire bonded to a commercial 850 nm photodiode. The capacitance of the photodiode is 0.24 pF. A commercial optical transceiver was used to measure the optical characteristics of the TIA. Figure 8 provides the relationship between the supply voltage and the total power dissipation. The power consumption scales from 2.8 to 4.69 mW when the supply voltage scales from 0.7 to 0.92 V. The results show that the total power consumption is propotional to the square of the supply voltage. This relationship confirms the power consumption saving possibility by voltage scaling/variation. A 2 31 -1 pseudorandom binary sequence input signal generated from Anritsu MP1763B pulse-pattern generator and an Aglient 86100 oscilloscope were used to measure the dynamic response. Figure 9 shows the observed eye diagrams of the TIA at 2.8, 5, and 6.135 Gbps at −4.3 dBm input power with the supply voltage of 0.7, 0.85, and 0.92 V, respectively. Figure 10 shows measured BER performance of the TIA at 2.5, 5, and 6.135 Gbps. The minimum input power required to get a BER of 10 −12 is −3 dBm at data rate of 6.135 Gbps. At 2.5 Gbps, in order to get BER of 10 −12 , an input power of −4.3 dBm is required. Table 1 shows the comparison of the proposed TIA with other works. Due to the operation in the weak or moderate inversion mode, the proposed TIA outperforms other TIA in terms of power consumption while maintaining high gain. At input supply voltage of 0.7-0.92, a low power consumption of 2.9-4.6 was achieved which is lower when compared to designs of similar technologies (as in [20,28]) and of lower technologies (as in [13,21,25]). Also the transimpedance gain is high when compared to designs of similar and lower technology. Based on the comparison of the proposed TIA with other works in Table 1, it can be seen that if designed in lower technology node, the proposed TIA has the potential to provide improved performance and a number of benefits associated with lower technology nodes.

CONCLUSION
An ultra-low power TIA with variable bandwidth has been proposed and implemented in this study. In order to reduce the power consumption, the TIA was implemented using RGC topology with capacitor degeneration for frequency enhancement in the weak inversion mode. With a supply voltage of the range 0.7-0.92 V, a reduced power consumption of 2.9-4.6 mW, and a variable bandwidth of the range 3-4.9 GHz were achieved. When packaged with a 850 nm photodiode, the measured results showed clear eye diagrams at 2.5-6.135 Gbps. A BER of less than 10 −12 with the input power of −4.3 dBm to −3 dBm at 2.5-6.135 Gbps, respectively, was achieved with a transimpedance gain of 51.2-52.4 dBΩ. The chip occupied a very small area of 0.28 × 0.42 mm 2 with pads and 0.1 × 0.1 mm 2 without pad. The designed TIA can be applied as a front-end circuit to convert the input photocurrent to output voltage that is high enough to feed to the next stages of an optical receiver such as the limiting amplifier stages (gain stages) and the output buffer, and is applicable for chip-to-chip optical interconnects.