Machine learning-based design automation of CMOS analog circuits using SCA-mGWO algorithm

Analog circuit design is comparatively more complex than its digital counter-part due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm ’ s efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the inter-change of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.


| INTRODUCTION
There is a significant increase in complexity while reducing the overall time-to-market of an integrated circuit due to the technology scaling and increased demand for electronics. Furthermore, increased nonlinearity makes achieving the global optimum solution at advanced technology nodes more difficult. Complex circuits at lower technology nodes increase the search space, necessitating the use of automated analog circuits design approaches.
Equation-based and simulation-based approaches are two of the most commonly used ways for design automation of complementary metal-oxidesemiconductors (CMOS) analog circuits, where the design equations and simulator are employed in the synthesis stage of circuit design, respectively. The stateof-the-art literature shows that metaheuristic algorithms such as particle swarm optimization (PSO) [1][2][3][4][5][6], greywolf optimization (GWO) [7,8] algorithm, enhanced version of GWO (EGWO) algorithm [9], whale optimization algorithm (WOA) [10][11][12], symbiotic organisms search algorithm [13], ALC-PSO algorithm [14,15] and a hybrid of WOA, and modified GWO (mGWO) algorithms (WOA-mGWO) [16] have been successfully applied and are used for the optimal design of various CMOS analog and radio frequency circuits using various design equations that help in developing the cost function and design constraints [17]. Similarly, different optimization algorithms are used for enhanced optimization of analog ICs using simulated results instead of derived results, such as hierarchical PSO (HPSO) [18] and PSO [19], a clustered gravitational search algorithm [20], GSA, advanced GSA (AGSA), and advanced GSA-PSO algorithms [21,22]. Additionally, many metaheuristic algorithms have also been used in various other challenging applications [23,24] This study proposes a novel hybrid algorithm using low-level teamwork hybridization of the sine-cosine algorithm (SCA) [25] and modified GWO (mGWO) [modifiedGWO] algorithms, and the same is validated for its efficiency and robustness when compared with other competing algorithms. The hybrid SCA-mGWO algorithm is applied for the design automation of an all-CMOS voltage reference circuit [26] with a β multiplier self-biasing current source. The design of the voltage reference circuit is also tested across corners for evaluating the overall robustness of the design.
The rest of the paper is organized as follows: Section 2 describes the hybridization of the SCA-mGWO algorithm. The validation and comparison of the proposed algorithm with other competing algorithms is presented in Section 3. The circuit description and formulation of the cost function are explained in Section 4. Section 5 discusses the simulation results and comparison. Finally, the paper is concluded in Section 6.

| THE HYBRID SCA-MGWO ALGORITHM
The SCA and mGWO algorithms are swarm intelligencebased algorithms inspired by mathematical models of sine-cosine functions and grey-wolf hunting behavior [22] and [15], respectively. The mGWO algorithm searches the entire search space globally, bringing most of the solutions to the favorable area. Then SCA searches for the best solution within that favorable area locally. The major emphasis of the mGWO algorithm is to explore the entire search area establishing the expansion at the starting point, whereas the SCA algorithm focuses on the enhanced search in the optimization process. This approach helps in dealing with global and local search processes simultaneously using the combined abilities of the metaheuristics.

| Optimization process of hybrid SCA-mGWO algorithm
This section explains the detailed optimization flow of the proposed hybrid SCA-mGWO algorithm ( Figure 1).
Step 1: The random vector is initialized as the beginning point of the optimization process with population size, N, and dimension, D.
where X (i, j ) is the jth dimension of ith solution; rand() is random number in the range [0, 1]; ub j and lb j are the upper and lower bounds with jth dimension, respectively.
Step 2: The fitness of the objective function is evaluated for each search agent, X (i, j) ; that is, the function's value is calculated over the entire population, resulting in the best position that will be used for the current search agent's position update for the next iteration.
Step 3: The algorithm parameters, such as r 1 , r 2 , r 3 , r 4 , A, a and C, are initialized.
F I G U R E 1 Optimization flow for SCA-mGWO algorithm where r i , (i = 1 to 4), are the random numbers from 0 to 1, Maxiter is the maximum number of iterations, t is the current iteration, and "Á" is the element-by-element multiplication.
Step 4: When A < 1, the position of the search agent is updated using the equations shown below. Xðt where D a , D b , and D d are the Euclidean distances between the current search agent and three best search agents, that is, alpha, beta, and delta, respectively. X 1 , X 2 , and X 3 are the positions of alpha, beta, and delta, respectively. Xðt þ 1Þ is the updated position of current search agent.
Step 5: When A > 1 and r 4 < 0.5, the position of the search agent is updated as follows.
Step 6: When A > 1 and r 4 ≥ 0.5, the position of the search agent is updated as follows.
where XðtÞ, X a ðtÞ, and Xðt þ 1Þ are the positions of current search agent, best search agent, and updated position of current search agent, respectively. r 1 , r 2 , and r 3 are the random numbers ranging from 0 to 1.
Step 7: Any violation in the control variable results in setting the value to lower or upper limit.
Step 8: If the termination criteria are not satisfied, continue from Step 3. Else, output the optimum solution.

| VALIDATION OF HYBRID SCA-MGWO ALGORITHM
The hybrid SCA-mGWO algorithm's efficiency is assessed by running several tests and comparing the results to those of other competing algorithms using a collection of 23 classical and popular functions as a benchmark [15]. The above-mentioned benchmark functions are evaluated using the proposed algorithm and compared to competing algorithms such as SCA, WOA, PSO, GWO, differential evolution (DE), and GSAPSO in over 20 independent runs. The parameters used to tune SCA, WOA, and GWO are r 1 , r 2 , r 3 , and r 4 , which are all random numbers. In PSO, the parameters c 1 and c 2 are set to 2; in DE, the mutation factor and crossover rate are 0.4-0.8 and 0.5, respectively; in GSAPSO, c 0 1 and c 0 2 are set to 0.5 and 1.5, respectively. Tables 1 and 2 report statistical analysis of the solutions obtained after the final iteration for a few of the 23 benchmark functions. The hybrid SCA-mGWO outperforms other algorithms on 4 out of 7, 4 out of 6, and 6 out of 10 functions for unimodal, multimodal, and multimodal high-dimensional benchmark functions, respectively, according to the results.
The comparison of the convergence rates for functions F1-F23 using SCA-mGWO and other competing algorithms have been investigated and the same for a few functions, that is, F 1 , F 2 , F 4 , and F 9 , is illustrated in Figure 2. The descending trend proves that the SCA-mGWO algorithm's ability to obtain global optimum solutions over 3000 iterations for each benchmark function. Overall, these results show the potential of the hybrid SCA-mGWO algorithm in solving problems that other algorithms cannot solve efficiently. The descending trend demonstrates the hybrid SCA-mGWO algorithm's ability to obtain a better global optimum solution over the course of iterations. Therefore, it is inferred that the SCA-mGWO algorithm results in better exploration to exploitation ratio while solving different optimization problems.
The algorithms cannot be compared for each individual run based solely on statistical values from 20 different runs. Hence, there is always a possibility that the predominance may have occurred by chance. The Wilcoxon statistical test is performed at 5% significance level, and the p values are compared for each run, and the significance of the results is decided, as shown in Table 3. For the statistical test, the best algorithm in each test function is compared with other algorithms independently. For example, if the best algorithm is SCA-mGWO, pairwise comparison is made between SCA-mGWO/SCA, SCA-mGWO/GWO, SCA-mGWO/PSO, and so forth. As shown in Table 3, p values for most of the functions are much less than 5% for the SCA-mGWO, demonstrating its statistical significance. The SCA-mGWO algorithm does not yield a p value greater than 0.05 for any of the functions, indicating that the SCA-mGWO algorithm is not similar to base algorithms or any other competing algorithm.

| ANALOG IC SIZING
An IC sizing tool for the automated design of analog circuits is presented in this section. The proposed tool,  Figure 3, uses the simulation-based methodology and the proposed SCA-mGWO algorithm in the synthesis and optimization sections, respectively. Note that the SPEC-TRE simulator simulates analog circuits, and a hybrid SCA-mGWO algorithm is implemented in MATLAB. The synthesis and optimization sections of this tool are connected through the interface between CADENCE and MATLAB. The process starts by determining the design parameters and constraints while reasonably selecting the predefined range for each design parameter. The initial population of the circuit parameters (N masses) is randomly generated, and the same is given to the synthesis section as a starting point of the design process. The initial design parameters are sent to the input file in the synthesis section. Then, the circuit is simulated using a specter considering the received inputs and saves the performance metrics to the output file. While evaluating the fitness, the proposed tool reads the output file and calculates the violation of each constraint. This utility then runs the SCA-mGWO optimization process to generate new design parameters for the following iteration. This process is continued until the termination criterion is satisfied. Finally, the optimal circuit sizing is found and reported for the analog circuit.

| Case study: CMOS voltage reference
The schematic of a CMOS voltage reference circuit with a current source and bias voltage subcircuits is shown in Figure 4. In the current source subcircuit with modified β multiplier self-biasing, a MOS resistor (MR 1 ) is used to replace the ordinary resistor while generating the current,

| Principle of operation
The operation of the circuit is described in this section. All the transistors are operated in the subthreshold region except for MR 1 which is in the linear/triode region. The subthreshold drain current (I D ) is an exponential function of V GS and drain-to-source voltage V D S .
where K is the aspect ratio of the transistor, μ is the carrier mobility, C OX is the gate-oxide capacitance, V T H is the threshold voltage thermal voltage, V T is the thermal voltage, and η is the subthreshold slope. The current, I D , tends to become independent of V DS with higher V DS , that is, if V DS > 0.1 V.
The gate-to-source voltage of M 1 , V GS1 , is equal to the sum of drain-to-source voltage of M 1 , V DS1 , and gate-tosource voltage of M 2 , V GS2 .
The current in M 1 and M 2 is equal to I P while MOS resistor MR 1 operating in deep triode region. The voltages V GS3 through V GS7 form a loop with the currents of 3I P and 2I P through transistors M 4 and M 6 , respectively. Thus, the output reference voltage is given by where V TH is the MOS threshold voltage, V T is the thermal voltage, K is the aspect ratio (W/L), and I P is the bias current. Since V T has positive TC and V TH has negative TC, zero TC can be obtained as the output voltage. The circuit's output voltage is equal to the threshold voltage of the MOS transistor at 0 K, and the TC is insensitive to process variations over different temperature ranges.

| Formulation of cost function
The cost function is calculated by considering both the constraints and the target that must be met when optimizing the circuit. The limitations are as follows: • Maintain the widths and lengths of current mirror transistors MC 1 , MC 2 and M 1 , M 2 .
• For proper matching, maintain the lengths and widths of transistors MC 1 , MC 2 , MC 3 , MC 4 , and MC 5 while changing the multipliers.
where mc 3 , mc 4 , and mc 5 are the multipliers of the transistors MC 3 , MC 4 , and MC 5 , respectively. • Avoid the currents less than the leakage currents, that is, 1 nA.
• For proper matching, maintain the widths and lengths of transistors M 3 , M 4 , M 5 , M 6 , and M 7 while modifying the multipliers.
where m 3 , m 4 , m 5 , m 6 , and m 7 are the multipliers of the transistors M 3 , M 4 , M 5 , M 6 , and M 7 , respectively. The major aim of the optimization is to reduce the overall variation of the output voltage across the range of temperature, that is, À40 C to 100 C, while satisfying all the constraints. The variation of the output reference voltage, VREF, across temperature is given by where V max and V min are the absolute maximum and absolute minimum of the difference between target and obtained V REF over the temperature range of À40 C through 100 C. Variation ðV REF Þ is the maximum of absolute maximum and absolute minimum voltages. The overall cost function is given by where P 1 , P 2 , P 3 , and P 4 are penalties for the (12) to (15), respectively.

| SIMULATION RESULTS
To validate the proposed SCA-mGWO algorithm, MATLAB (R2017a) on Intel core i3-4010U CPU @ 1.70 GHz processor with 12 GB RAM was used. Besides, the algorithm's automation methodology is tested using CADENCE (IC6.1.8) in a 40-nm standard process with all-CMOS voltage regulators as a benchmark. The targeted reference voltage is 550 mV with constraints on the currents in each mirror to be greater than 1 nA for F I G U R E 2 Convergence plots for functions F 1 , F 2 , F 4 , and F 9 avoiding the effect of leakage currents, avoiding minimum dimensions to reduce mismatch, and matching in the current mirrors. The range for the lengths and multipliers is from 1 μm to 20 μm and from 1 to 100, respectively. For proper matching, the widths of the transistors are maintained constant at 1 μm. The design parameters obtained using the SCA-mGWO algorithm are demonstrated in Table 4, which also shows that the maximum multiplier value obtained is 47 μm, making the maximum total width of the transistors to be 47 μm.
The convergence plot of the SCA-mGWO algorithm for the variation of reference voltage in CMOS voltage regulator is illustrated in Figure 5 with the minimum variation of 0.85%. The convergence plot also shows that the proposed algorithm results in the optimum solution at 24th iteration proving its efficiency in solving analog circuit sizing problems.  Table 5 demonstrates the numerical results depicting the reference voltage (V REF ), minimum and maximum differences with respect to V REF , that is, V min and V max and the percentage variation obtained using SCA-mGWO and its comparison with other competing algorithms.
The divergence of V REF with respect to a temperature range of [À40 100] at different corners, that is, typical (TT), slow slow (SS), slow fast (SF), fast slow (FS), and fast fast (FF), shown in Figure 6, demonstrates that the maximum absolute variation of V REF across all corners with respect to V Target , that is, 550 mV, is 4%.
The robustness of the design is also evaluated using by varying the V dd to obtain the variation in V REF . Figures 7-11 illustrate the variations of the V REF with temperature at parameterized V dd , that is, 4 V, 4.4 V, 4.8 V, 5.2 V, 5.6 V, and 6 V, across TT, SS, FF, SF, and FS corners. Figure 12 shows the percentage variation of the output reference voltage with respect to V dd across different corners. It depicts that the maximum variation is obtained for the FF corner while the minimum variation is observed for the SF corner. The reference voltage as a function of V dd , at room temperature, is also shown in Figure 12. The operation of the circuit starts at the supply voltage, starting at 2 V.
Monte  The simulation results and Monte Carlo analysis show the robustness of the circuit designed with the SCA-mGWO algorithm, as well as the efficiency of the proposed automation methodology. The examination across the corners confirms the output voltage's consistency while proving the SCA-mGWO algorithm's stability, which is possible when a significant balance between exploration and exploitation is maintained.

| CONCLUSION
The automation of CMOS analog circuits has become important to cope with the increased pace of technology scaling and reduced time-to-market of the entire IC. In this paper, a novel SCA-mGWO algorithm is applied in the optimization section of the automation process. The SCA-mGWO algorithm is validated using benchmark functions, and the SCA-mGWO algorithm outperforms competing algorithms for 14 functions. The SCA-mGWO algorithm-based optimization methodology is evaluated using a case study with a CMOS voltage reference circuit. The optimum design parameters obtained using the optimization algorithm are implemented in CADENCE. The simulation results demonstrate that the design can obtain the variation of 0.85% over the temperature range of À40 C through 100 C. The circuit is also tested for its efficiency over different corners, that is, TT, SS, SF, FF, and FS, and the overall variation across corners is obtained to be 4%. Also, the Monte Carlo analysis is performed to evaluate the design's robustness, obtained using the SCA-mGWO algorithm, resulting in a standard deviation of variation of 70.78 m%. To further sophisticate the process, a multiobjective optimization algorithm with advanced constraint handling techniques can be used in the presented approach.